Paul H. Bardell

Design considerations for parallel pseudorandom pattern generators

The design of a Parallel (pseudo)Random Pattern Generator (PRPG) based on a Linear Feedback Shift Register (LFSR) involves the selection of the number of stages (degree of the characteristic polynomial), selection of the feedback taps (the characteristic polynomial), and selection of a phaseshift network to remove the effects of correlations that exist between the bit streams from adjacent stages of the LFSR. The design considerations for decimated sequences are discussed, as is linear dependency density. A new phaseshift network is presented which uses only one 2-way EXCLUSIVE-OR per output. Appendixes contain a listing of the prime factors of the sequence length, an exhaustive list of primitive trinomials to degree 100, and a selected list of primitive polynomials that can be used to realize LFSRs with only two 2-way EXCLUSIVE-ORs.

Production experience with built-in self-test in the IBM ES/9000 system

This paper describes the performance of the Self-Test System used in the production of circuit modules for the new line of mainframes, the ES/9000 series. The system supports pseudorandom patterns generated and applied in a self-test mode from within the module, as well as control and pseudorandom stimuli and response compression through the IjO pins. Simulation-based diagnostics are used to generate repair actions to specific micro-nets, with an associated confidence level. Modules (containing roughly 500,000 gates) are being verified in under 3 minutes, with diagnosis of failing modules resulting in the isolation of a fault with 5 minutes of on-line time, followed by 11.7 minutes of off-line analysis.

Calculating the effects of linear dependencies in m-sequences used as test stimuli

When pseudorandom patterns generated by a linear feedback shift register (LFSR) are used as test stimuli, there is always a concern about the linear dependencies within the sequence of patterns. It is possible for these linear dependencies to preclude a specific test pattern from being present in the sequence of applied patterns. These dependencies and ways to calculate their effects on a particular test are discussed, with the goal of developing the means of analyzing a digital circuit which is connected to a source of pseudorandom patterns to determine whether or not linear dependencies are encountered by a particular connection. >

Built-In Self-Test: Milestones and Challenges

This paper describes the progress in built-in self-test (BIST) since its inception, and the important problems that still need to be solved to make the technique widely acceptable. The paper includes a reference list and an extensive bibliography on the subject matter.

Primitive polynomials of degree 301 through 500

This letter is an extension of the table of minimal weight primitive polynomials found in [1].

Discrete logarithms: a parallel pseudorandom pattern generator analysis method

The phaseshifts between the bitstreams emitted from various stages of one-dimensional linear finitestate machines are analyzed. An operational calculus involving ashift operator is developed. The concept of discrete lograithms of binary polynomials is introduced to calculate phaseshifts. The analysis technique is applied to various examples of cellular automata and LFSRs. Phaseshift end effects are observed in cellular automata due to rule configurations. Modified LFSR generators are shown to have potentially more useful outputs than cellular automata, lower circuit complexity, and equivalent phaseshift statistics.

Partitioning of polynomial tasks: test generation, an example

The circumstances under which a partitioning of a task with a polynomial complexity will result in an overall reduction of its execution time are analyzed. It is assumed that the task executor is sequential in nature, namely it can execute only one task at a time. Since partitioning of a task into smaller subtasks will, most probably, result in subtask overlap, there is a risk that a given partitioning scheme will yield an increase in its overall execution time. Formulas are derived to test the effectiveness of any proposed partitioning scheme. In the case of multiple partitioning options, the best one can be easily obtained. One of the possible tasks that this analysis is applicable to is the test generation of digital circuits with a uniprocessor. >