Paul Hundt

Thermal performance of tape based ball grid array over molded packages

A near chip scale package based on area array technology with a tape interposer is thermally evaluated using both computer models and measurement techniques. The package is described and compared to the thermal performance of QFPs with comparable physical dimensions. The thermal performance of the package has been found to be highly dependent upon the arrangement of the solder balls on the interposer and on the die size. The impact of thermal solder balls and underfill is investigated, the contribution of a heat spreader is described, and thermal variation with material composition is studied.

Characterizing Bulk Thermal Conductivity and Interface Contact Resistance Effects of Thermal Interface Materials in Electronic Cooling Applications

Thermal Interface Materials (TIMs) are used as thermally conducting media to carry away the heat dissipated by an energy source (e.g. active circuitry on a silicon die). Thermal properties of these interface materials, specified on vendor datasheets, are obtained under conditions that rarely, if at all, represent real life environment. As such, they do not accurately portray the material thermal performance during a field operation. Furthermore, a thermal engineer has no a priori knowledge of how large, in addition to the bulk thermal resistance, the interface contact resistances are, and, hence, how much each influences the cooling strategy. In view of these issues, there exists a need for these materials/interfaces to be characterized experimentally through a series of controlled tests before starting on a thermal design. In this study we present one such characterization for a candidate thermal interface material used in an electronic cooling application. In a controlled test environment, package junction-to-case, Rjc, resistance measurements were obtained for various bondline thicknesses (BLTs) of an interface material over a range of die sizes. These measurements were then curve-fitted to obtain numerical models for the measured thermal resistance for a given die size. Based on the BLT and the associated thermal resistance, the bulk thermal conductivity of the TIM and the interface contact resistance were determined, using the approach described in the paper. The results of this study permit sensitivity analyses of BLT and its effect on thermal performance for future applications, and provide the ability to extrapolate the results obtained for the given die size to a different die size. The suggested methodology presents a readily adaptable approach for the characterization of TIMs and interface/contact resistances in the industry.Copyright

Wafer level packaging of a tape flip-chip chip scale packages

Abstract The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment. Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen. This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.

Tacky Dots/sup TM/ transfer of solder spheres for flip chip and electronic package applications

The use of preformed solder spheres for bumping flip chip wafers has not gained wide acceptance within the semiconductor industry. Due in part to equipment shortcomings, solder sphere transfer until now was commonly limited to spheres 300 /spl mu/m or larger, much too large for the typical flip chip applications of 150 /spl mu/m or less. To address this need, Texas Instruments and DuPontB have jointly developed a process for transferring 127 /spl mu/m diameter solder spheres to wafers. The process, called Tacky Dots/sup TM/, forms are array of sticky or tacky dots in a photoimageable adhesive coating. Solder spheres sprinkled on the adhesive coating are then captured and retained by the tacky dots until the spheres are aligned and reflowed to the wafer. This paper describes the equipment and processes developed for bumping wafers using Tacky Dots/sup TM/. The compliant polyimide sheet used in Tacky Dots/sup TM/ required a new and unique equipment design that aligns the solder spheres to the wafer and then reflows the solder without moving the wafer. Post reflow analysis of the bumped dies before and after environmental testing is reviewed. Tests conducted with a leadless chip carrier package design are also reviewed to demonstrate the capability of Tacky Dots/sup TM/ at transferring spheres to electronic packages and substrates other than wafers.

Evaluation of and Inspection Metrology for Lid Attach for Advanced Thermal Packaging Materials

We have evaluated a new Ag-filled silicone thermal interface material (TIM) for its sensitivity to lid finish and impact on imaging discontinuities in the die/lid (TIM1) layer, in conjunction with two high performance lid materials, as a part of our advanced packaging technology development effort. Thermal and mechanical (shear stress and lid pull) measurements have been carried out on a number of different lid finishes to optimize thermal performance and adhesion at the TIM1/lid interface. This silicone TIM1 is found to be sensitive to the type of Ni-plating and plating bath chemistry. Nondestructive and destructive metrology has been carried out on flip chip (FC) packages using Ag-filled silicone TIM1 and either Cu or AlSiC lids. A number of silicone formulations have been investigated to assess their impact on surface acoustic microscopy (SAM) and X-ray imaging. Nondestructive evaluation (NDE) by real time X-ray and SAM has identified artifacts that make it difficult to unambiguously detect voids and delamination in the TIM1 layer. A “dark ring” or “picture frame” artifact is observed at the die perimeter in acoustic microscope images of packages with the Ag-filled TIM1. Detailed SEM cross-section and thermal mapping analyses on a number of specially constructed FC packages have been correlated with TIM1/lid delamination and voiding observed in SAM and X-ray images. Results of these studies point to changes in the TIM1 modulus during cure and post cure thermal excursions as the cause of the “dark ring” observed in the transmission SAM images rather than delamination at the TIM1/lid or TIM1/die interfaces. However, in the event that delamination is present at the edges it cannot be unambiguously deconvoluted from the “dark ring” artifact in the SAM images.Copyright

Development Status of High Speed Ball Pull for Pb-Free BGA Characterization

Current methods for characterizing the integrity of BGA solder ball attachment include both ball shear and ball pull. These are currently limited to slow speeds, 5 mm/second for pull and 0.6 mm/second for shear. The results from these tests are of limited use in predicting brittle failures that are sometimes seen early in product lifetime. This paper will discuss the status of our work on implementing the highspeed ball pull test that should be of much greater utility in highlighting brittle failure modes. A JEDEC standard, JESD 22-B115, has recently been published that governs solder ball pull test methods. In this paper, the software and hardware set-up for high speed ball pull will be described and its limitations and operating window will be discussed. The various failure modes for high speed pull will be illustrated along with set-up issues that can impact the failure mode. The response variables for this test include peak force and fracture energy. Force-distance plots will also be shown and correlated test hardware / set-up issues. Finally issues associated with using this test as a process monitor will be discussed.

Tacky Dots/sup TM/ technology for flip chip and BGA solder bumping

As the electronics market moves toward higher performance Integrated Circuits (ICs), each IC requires larger numbers of Inputs and Outputs (I/Os). This has resulted in a strong need in the marketplace for a low cost, high resolution method for placing controlled volumes of solder (or other metal alloys) on bond pads of ICs and area array semiconductor packages, such as Ball Grid Arrays (BGAs), and Chip Scale Packages (CSPs). To satisfy this need, DuPont has developed the concept of Tacky Dots/sup TM/, which utilizes proprietary technology in photoimageable adhesives to form a pattern of tacky areas, which are subsequently populated with conductive particles and then transferred to ICs or packages. DuPonts expertise and effort have been focused on developing a systems approach to the front end population process, while working closely with Texas Instruments who has developed technology to enable the effective transfer of the conductive particles. This paper contains details of the imaging and population technology as well as a discussion of the overall progress of this new wafer bumping process.