Paul M. Chau

Image encryption for secure Internet multimedia applications

We present a novel scheme for secure Internet image transmission. The feature of the proposed scheme is joint application between image compression and image encryption. For source coding, we implement the discrete wavelet transform (DWT) and for channel coding, we utilize the block cipher Data Encryption Standard (DES) algorithm. Simulation results show that our proposed method significantly enhances security for image transmission over Internet as well as improves the transmission rate.

A technique for realizing linear phase IIR filters

A real-time IIR filter structure is presented that possesses exact phase linearity with 10 approximately 1000 times fewer general multiplies than conventional FIR filters of similar performance and better magnitude characteristics than equiripple or maximally flat group delay IIR filters. This structure is based on a technique using local time reversal and single pass sectioned convolution methods to realized a real-time recursive implementation of the noncausal transfer function H(z/sup -1/). The time reversed section technique used to realize exactly linear phase IIR filters is described. The effects of finite section length on the sectional convolution are analyzed. A simulation methodology is developed to address the special requirements of simulating a time reversed section filter. A design example is presented, with computer simulation to illustrate performance, in terms of overall magnitude response and phase linearity, as a function of finite section length. Nine example filter specifications are used to compare the performance and complexity of the time reversed section technique to those of a direct FIR implementation. >

Macro pipelining based scheduling on high performance heterogeneous multiprocessor systems

Presents a technique for pipelining heterogeneous multiprocessor systems, macro pipelining based scheduling. The problem can be identified as a combination of optimal task/processor assignment to pipeline stages as well as a scheduling problem. The authors propose a new technique based on iterative applications of partitioning and scheduling schemes whereby the number of pipeline stages are identified and the scheduling problem is solved. The pipeline cycle is optimized in two steps. The first step finds a global coarse solution using the ratio cut partitioning technique. This is subsequently improved by the iterative architecture driven partitioning and the repartitioning and time axis relabeling techniques of the second step. The authors have considered a linear interprocessor communication cost model in scheduling. The proposed technique is applied to several examples. They find that for these examples, the proposed macro pipelining based scheduling can improve the throughput rate several times that of the conventional homogeneous multiprocessor scheduling algorithms. >

A model for estimating power dissipation in a class of DSP VLSI chips

A high-level power dissipation model for filter- and transform-type digital signal processing (DSP) algorithms implemented using linearly connected multiply-add-based processing elements is presented. Exploration of alternative algorithms, architectures, and design styles for a given signal processing task in terms of high-level parameters is possible using this model. It is shown that there is often an optimal selection of the number and type of time-shared processing elements for VLSI implementation that minimizes the overall power dissipation. A major application of the proposed model is to make quantitative evaluations for exploration of alternative DSP algorithms and architectures. When combined with previously developed area-time metrics, the proposed power dissipation model permits a more realistic evaluation of new and existing circuit solutions to DSP tasks. >

Prime: A Timing-Driven Placement Tool Using A Piecewise Linear Resistive Network Approach

An approach toward path-oriented timing-driven placement is proposed. We first transform the placement with timing constraints to a Lagrange problem. A primal-dual approach is used to find the optimal relative module locations. In each primal dual iteration, the primal problem is solved by a piecewise linear resistive network method, while the dual process is used to update the Lagrange multiplier. The sparsity of the piecewise linear resistive network is exploited to obtain dramatic improvement on the efficiency of the calculation. Up to 22.0% of clock cycle reduction was observed for Primary2 test case.

A radial basis function neurocomputer implemented with analog VLSI circuits

An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.<<ETX>>

A wire length estimation technique utilizing neighborhood density equations

A new wire length estimation technique is presented. Wire length distribution is modeled by wire density on a 2-D lattice. Assuming a pointwise independent branching process, the wire length distribution is found by solving the neighborhood density equations. For several industrial circuits tested, this technique achieved an estimation error of 9.0% with a maximum deviation of +16.3%, which compared favorably with other techniques recently proposed.<<ETX>>

Conditional probability density function estimation with sigmoidal neural networks

Real-world problems can often be couched in terms of conditional probability density function estimation. In particular, pattern recognition, signal detection, and financial prediction are among the multitude of applications requiring conditional density estimation. Previous developments in this direction have used neural nets to estimate statistics of the distribution or the marginal or joint distributions of the input-output variables. We have modified the joint distribution estimating sigmoidal neural network to estimate the conditional distribution. Thus, the probability density of the output conditioned on the inputs is estimated using a neural network. We have derived and implemented the learning laws to train the network. We show that this network has computational advantages over a brute force ratio of joint and marginal distributions. We also compare its performance to a kernel conditional density estimator in a larger scale (higher dimensional) problem simulating more realistic conditions.

CUSP: A 2-/spl mu/m CMOS Digital Signal Processor

This paper describes the Cornell University Signal Processor (CUSP), a 60 000 transistor 2-/spl mu/m CMOS processor custom designed to compute the Fast Fourier Transform (FFT) and related algorithms. Operating on a 50-MHz clock, the bit-serial arithmetic hardware on a CUSP chip performs over 15 million 20 X 20 bit multiplications per second and computes a 1024 point FFT in 1.33 ms. The chip architecture is presented along with a description of the arithmetic, control, and fault detection circuitry. The inclusion of these components on a single chip is shown to allow large fault tolerant arrays of CUSP processors to be efficiently employed for high-performance applications.

CMOS VLSI implementation of gigabyte/second computer network links

High speed computer network links require a variety of on-chip system components in order to achieve optimal performance. These components include systems that provide clock generation and synchronization as well as line driver and receiver circuits for signal conditioning. This paper presents designs for a link synchronizer, a low voltage differential signal (LVDS) I/O system, and a phase locked loop for providing a system clock. Portions of these systems have been implemented in 2 /spl mu/m and 1.2 /spl mu/m MOSIS chips.