Ronald D. Fellman

Prospective reliability of the STRokE DOC wireless/site independent telemedicine system.

The San Diego wireless telemedicine stroke evaluation arrangement described by Meyer et al.1 is unusual. Our similar REACH (Remote Evaluation of Acute isCHemic stroke) system at the Medical College of Georgia (MCG) uses secure Internet connections to evaluate acute stroke patients in rural hospitals of north central Georgia in the Nations “stroke belt.” Like the San Diego system, REACH uses any broadband (DSL or cable modem) Internet accessible computer, nationwide. However, without a broadband wireless bubble over Augusta, Georgia, consulting …The authors evaluated a site-independent telemedicine system. Telemedicine may be limited by the need for fixed connectivity. Wireless and site-independent technologies eliminate this limitation. Twenty-five stroke patients underwent evaluations by remote and bedside examiners. Ten of 15 (67%) NIH Stroke Scale and 9 of 11 (82%) Modified NIH Stroke Scale items showed excellent interrater reliability. Spearman correlations were > or =0.93. This Internet system is reliable and valid. Further studies should assess its use in acute stroke.

Macro pipelining based scheduling on high performance heterogeneous multiprocessor systems

Presents a technique for pipelining heterogeneous multiprocessor systems, macro pipelining based scheduling. The problem can be identified as a combination of optimal task/processor assignment to pipeline stages as well as a scheduling problem. The authors propose a new technique based on iterative applications of partitioning and scheduling schemes whereby the number of pipeline stages are identified and the scheduling problem is solved. The pipeline cycle is optimized in two steps. The first step finds a global coarse solution using the ratio cut partitioning technique. This is subsequently improved by the iterative architecture driven partitioning and the repartitioning and time axis relabeling techniques of the second step. The authors have considered a linear interprocessor communication cost model in scheduling. The proposed technique is applied to several examples. They find that for these examples, the proposed macro pipelining based scheduling can improve the throughput rate several times that of the conventional homogeneous multiprocessor scheduling algorithms. >

A VLSI priority packet queue with inheritance and overwrite

Reliable priority-based flow-control is essential for real-time applications involving hard-deadlines. However, the use of first-in-first-out (FIFO) queues in such systems introduces priority inversion resulting in unbounded transmission delays. For this reason, a priority transmission queue is critical for multimedia and mission-critical systems. Yet very few priority queue implementations exist. This paper presents the design of a novel VLSI priority packet queue (PPQ), implemented in 1.2 /spl mu/m CMOS technology. It achieves fast operation by manipulating its contents in terms of packet segments, rather than individual words. Similar to paged memory, this new segmented architecture greatly reduces implementation cost by reusing segments and avoiding storage area fragmentation. By distributing the computationally intensive priority comparison operation over the access time for an entire segment, the PPQ achieves 96% of the speed of a high-speed packet FIFO. The PPQ can either perform priority inheritance or overwrite lower priority packets to minimize the impact of queue overflow. In addition, it is suitable as a general computer network interface buffer, since it robustly handles asynchronous read and write clocks of greatly disparate frequencies. Our initial implementation achieves well over twice the speed of a nonpipelined approach with minimal additional overhead. Furthermore, scaling this design to larger capacities and more priority levels results in an even greater improvement in speed over conventional approaches. >

The STRokE DOC trial technique: ‘video clip, drip, and/or ship’

Rationale To describe the clinical trial methods of a site-independent telemedicine system used in stroke. Aims A lack of readily available stroke expertise may partly explain the low rate of rt-PA use in acute stroke. Although telemedicine systems can reliably augment expertise available to rural settings, and may increase rt-PA use, point-to-point systems do require fixed base stations. Site-independent systems may minimize delay. The STRokE DOC trial assesses whether site-independent telemedicine effectively and efficiently brings rt-PA to a remote population. Design STRokE DOC is a 5–year, 400–participant, noninvasive trial, comparing two consultative techniques at four remote sites. Participants are randomized to acute ‘STRokE DOC telemedicine’ or ‘telephone’ consultations. Treatment decision accuracy is adjudicated at two time points, using three levels of data availability and an independent auditor. Study outcomes The primary outcome measure is whether there was a ‘correct decision to treat or not to treat using rt-PA’ at each of three adjudication levels (primarily at Level #2). Secondary outcomes include the number of thrombolytic recommendations, intracerebral hemorrhage, and 90–day outcomes. Using the STRokE DOC system (or telephone evaluation), medical history, neurologic scales, CT interpretations, and recommendations have been completed on over 200 participants to date. Of the initial 11, nonrandomized, ‘run-in’ patients, six (65%) were evaluated wirelessly, and five (45%) were evaluated with a site-independent LAN or cable modem. Three (27%) received rt-PA. The adjudication methodology was able to show both agreements and disagreements in these 11 cases. It is feasible to perform site-independent stroke consultations, and adjudicate those cases, using the STRokE DOC system and trial design. Telemedicine efficacy remains to be proven.

Performance analysis of a fractal modulation communication system

Recent work has suggested the possibility and potential gains of using homogeneous signals, which can be represented in terms of orthonormal wavelet basis sets, as the modulating waveforms in communication systems. We present performance analysis, in terms of both bandwidth efficiency and probability of error, for one communication system where a fractal modulated signal is transmitted over a sinusoidal carrier. In addition, we present some preliminary results from a fractal modulation simulator indicating that a practical implementation is quite feasible while maintaining near-theoretical performance for the test case of transmission over the additive white Gaussian noise (AWGN) channel. Preliminary results indicate that fractal modulation achieves a reasonable improvement over some existing modulation schemes.

CMOS VLSI implementation of gigabyte/second computer network links

High speed computer network links require a variety of on-chip system components in order to achieve optimal performance. These components include systems that provide clock generation and synchronization as well as line driver and receiver circuits for signal conditioning. This paper presents designs for a link synchronizer, a low voltage differential signal (LVDS) I/O system, and a phase locked loop for providing a system clock. Portions of these systems have been implemented in 2 /spl mu/m and 1.2 /spl mu/m MOSIS chips.

An extension to the SCI flow control protocol for increased network efficiency

The scalable coherent interface (SCI) is a newly established IEEE standard that provides bus-like services to a network of nodes without actually using a physical bus. Rather, it utilizes very fast, unidirectional links that can be arranged into a variety of topologies. SCI provides a novel fairness protocol that equally allocates bandwidth to all nodes on the network. When global fairness is not required, it is often desirable to relax its enforcement, in exchange for increased network utilization and better load balancing. This paper presents an extension to the SCI flow control protocol that increases network utilization and, hence, attainable system throughput by enforcing fairness only among nodes whose transmissions interfere with one another. The enhanced protocol grants a node as much bandwidth as it requires, as long as its transmissions do not inhibit those of other nodes. Although this is commonly known as max-min fairness, we more descriptively refer to it as relaxed fairness. We present extensive simulation results and compare them to the standard SCI protocol and to our desired performance, which has been preciously derived in the literature. The comparisons show that, on average, this enhancement can provide a substantial increase in performance over the original protocol.

Improved scheduling of signal flow graphs onto multiprocessor systems through an accurate network modelling technique

This paper presents a new integrated technique for accurately scheduling acyclic precedence expansion graphs (APEGs) onto multiprocessor networks with various topologies. APEGs specify the nature, connectivity, and precedence relationships of all tasks, as well as data amounts that pass between tasks. We present a scheduling algorithm that uses the Branch and Bound technique when the number of tasks in the graph is small, and the Earliest Task First heuristic, otherwise. Graph partitioning and scheduling algorithms however, require a good estimate of interprocessor communication (IPC) costs within the target network. We thus use a technique called Successive Superposition to accurately determine IPC costs. Successive Superposition provides a methodology to decompose a complex network, containing primarily deterministic traffic, into simpler queueing models which may then be analyzed in isolation. By combining a heuristic scheduling algorithm with this exact IPC analysis technique, we avoid unpredictable behavior and incorrect mapping decisions that could result in longer graph execution times. We present an example in which an inaccurate assessment of IPC costs leads to a 22% to 30% increase in the graph execution time.

Enhancing SCI's fairness protocol for increased throughput

The scalable coherent interface (SCI) is a newly established IEEE standard which provides bus-like services to a network of nodes connected by very fast, unidirectional links. SCI provides an efficient flow control protocol that fairly allocates bandwidth to all nodes on the network. When global fairness is not required, it is desirable to relax its enforcement, in exchange for increased network utilization. This paper presents an extension to SCIs fairness protocol that increases attainable throughput by enforcing fairness only among conflicting nodes. The authors present extensive simulation results and compare them to the standard SCI protocol and to the desired performance, which is derived in the paper. The comparisons show that, on average, the enhancements substantially increase the performance of the original protocol.<<ETX>>

Design and evaluation of an architecture for a digital signal processor for instrumentation applications

The authors present the design and evaluation of an architecture for a monolithic, programmable, floating-point digital signal processor (DSP) for instrumentation applications. An investigation of the most commonly used algorithms in instrumentation led to a design that satisfies the requirements for high computational and I/O (input/output) throughput. In the arithmetic unit, a 16*16-bit multiplier and a 32-bit accumulator provide the capability for single-cycle multiply/accumulate operations, and three format adjusters automatically adjust the data format for increased accuracy and dynamic range. An on-chip I/O unit is capable of handling data block transfers through a direct memory access port and real-time data streams through a pair of parallel I/O ports. I/O operations and program execution are performed in parallel. In addition, the processor includes two data memories with independent addressing units, a microsequencer with instruction RAM, and multiplexers for internal data redirection. The authors also present the structure and implementation of a design environment suitable for the algorithmic, behavioral, and timing simulation of a complete DSP system. Various benchmarking results are reported. >