Paul Theo Gonciari

Variable-length input Huffman coding for system-on-a-chip test

This paper presents a new compression method for embedded core-based system-on-a-chip test. In addition to the new compression method, this paper analyzes the three test data compression environment (TDCE) parameters: compression ratio, area overhead, and test application time, and explains the impact of the factors which influence these three parameters. The proposed method is based on a new variable-length input Huffman coding scheme, which proves to be the key element that determines all the factors that influence the TDCE parameters. Extensive experimental comparisons show that, when compared with three previous approaches, which reduce some test data compression environments parameters at the expense of the others, the proposed method is capable of improving on all the three TDCE parameters simultaneously.

Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression

This paper proposes a new test data compression/decompression method for systems-on-a-chip. Themethod is based on analyzing the factors that influencetest parameters: compression ratio, area overhead and testapplication time. To improve compression ratio, the newmethod is based on a Variable-length Input Huffman Coding(VIHC), which fully exploits the type and length of the patterns,as well as a novel mapping and reordering algorithmproposed in a pre-processing step. The new VIHC algorithmis combined with a novel parallel on-chip decoder that simultaneouslyleads to low test application time and low areaoverhead. It is shown that, unlike three previous approaches[2, 3, 10] which reduce some test parameters at the expenseof the others, the proposed method is capable of improvingall the three parameters simultaneously. For example, theproposed method leads to similar or better compression ratiowhen compared to frequency directed run-length coding[2], however with lower area overhead and test applicationtime. Similarly, there is comparable or lower area overheadand test application time with respect to Golomb coding [3],with improvements in compression ratio. Finally, there issimilar or improved test application time when comparedto selective coding [10], with reductions in compression ratioand significantly lower area overhead. An experimentalcomparison on benchmark circuits validates the proposedmethod.

Synchronization overhead in SOC compressed test

Test data compression is an enabling technology for low-cost test. Compression schemes however, require communication between the system under test and the automated test equipment. This communication, referred to in this paper as synchronization overhead, may hinder the effective deployment of this new test technology for core-based systems-on-chip. This paper analyzes the sources of synchronization overhead and discusses the different tradeoffs, such as area overhead, test time and automatic test equipment extensions. A novel scalable and programmable on-chip distribution architecture is proposed, which addresses the synchronization overhead problem and facilitates the use of low cost testers for manufacturing test. The design of the proposed architecture is introduced in a generic framework, and the implementation issues (including the test controller and test set preparation) have been considered for a particular case.

A compression-driven test access mechanism design approach

Driven by the industrial need for low-cost test methodologies, the academic community and the industry alike have put forth a number of efficient test data compression (TDC) methods. In addition, the need for core-based System-on-a-Chip (SoC) test led to considerable research in test access mechanism (TAM) design. While most previous work has considered TAM design and TDC independently, this work analyzes the interrelations between the two, outlining that a minimum test time solution obtained using TAM design will not necessarily correspond to a minimum test time solution when compression is applied. This is due to the dependency of some TDC methods on test bus width and care bit density, both of which are related to test time, and hence to TAM design. Therefore, this paper illustrates the importance of considering the characteristics of the compression method when performing TAM design, and it also shows how an existing TAM design method can be enhanced toward a compression-driven solution.

Integrated test data decompression and core wrapper design for low-cost system-on-a-chip testing

This paper discusses an integrated solution for reducing the volume of test data for deterministic system-on-a-chip testing. The proposed solution is based on a new test data decompression architecture which exploits the features of a core wrapper design algorithm targeting the elimination of useless test data. The compressed test data can be transferred from the automatic test equipment to the on-chip decompression architecture using only one test pin, thus providing an efficient reduced pin count test methodology for multiple scan chains-based embedded cores. In addition to reducing the volume of test data, the proposed solution decreases the control overhead, test application time and power dissipation during scan. Further, it also requires lower on-chip area when compared to the testing scenarios which employ decompression architectures for every scan chain and it eliminates the synchronization overhead between the automatic test equipment and the system-on-a-chip. Moreover, the proposed solution is scalable and programmable and, since it can be considered as an add-on to a test access mechanism of a given width, it provides seamless integration with any design flow. Thus, the proposed integrated solution is an efficient low-cost test methodology for systems-on-a-chip.

Useless memory allocation in system-on-a-chip test: problems and solutions

Unlike the existing research direction that focuses on useful test data reduction, this paper analyzes the useless test data memory requirements for system-on-a-chip test. The proposed solution to minimize the useless test memory is based on a new test methodology which combines a novel core wrapper design algorithm with a new test vector deployment procedure stored in the automatic test equipment (ATE). To reduce memory requirements, the proposed core wrapper design finds the minimum number of wrapper scan chain partitions such that the useless memory allocation is minimized in each partition, which facilitates efficient usage of ATE capabilities. Further the new test vector deployment procedure provides a seamless integration with the ATE. When compared to the previously proposed core wrapper design algorithms, the proposed test methodology reduces the memory requirements up to 45%, without any penalties in test area overhead.

Test Data Compression: The System Integrator's Perspective

Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but also the bandwidth requirements. In this paper we provide a quantitative analysis of two distinctive TDC methods from the system integrators standpoint considering a core based SOC environment. The proposed analysis addresses four parameters: compression ratio, test application time, area overhead and power dissipation. Based on our analysis, some future research directions are given which can lead to an easier integration of TDC in the SOC design flow and to further improve the four parameters.