Bashir M. Al-Hashimi

Variable-length input Huffman coding for system-on-a-chip test

This paper presents a new compression method for embedded core-based system-on-a-chip test. In addition to the new compression method, this paper analyzes the three test data compression environment (TDCE) parameters: compression ratio, area overhead, and test application time, and explains the impact of the factors which influence these three parameters. The proposed method is based on a new variable-length input Huffman coding scheme, which proves to be the key element that determines all the factors that influence the TDCE parameters. Extensive experimental comparisons show that, when compared with three previous approaches, which reduce some test data compression environments parameters at the expense of the others, the proposed method is capable of improving on all the three TDCE parameters simultaneously.

Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression

This paper proposes a new test data compression/decompression method for systems-on-a-chip. Themethod is based on analyzing the factors that influencetest parameters: compression ratio, area overhead and testapplication time. To improve compression ratio, the newmethod is based on a Variable-length Input Huffman Coding(VIHC), which fully exploits the type and length of the patterns,as well as a novel mapping and reordering algorithmproposed in a pre-processing step. The new VIHC algorithmis combined with a novel parallel on-chip decoder that simultaneouslyleads to low test application time and low areaoverhead. It is shown that, unlike three previous approaches[2, 3, 10] which reduce some test parameters at the expenseof the others, the proposed method is capable of improvingall the three parameters simultaneously. For example, theproposed method leads to similar or better compression ratiowhen compared to frequency directed run-length coding[2], however with lower area overhead and test applicationtime. Similarly, there is comparable or lower area overheadand test application time with respect to Golomb coding [3],with improvements in compression ratio. Finally, there issimilar or improved test application time when comparedto selective coding [10], with reductions in compression ratioand significantly lower area overhead. An experimentalcomparison on benchmark circuits validates the proposedmethod.

Considering power variations of DVS processing elements for energy minimisation in distributed systems

Dynamic voltage scaling (DVS) is a powerful technique to reduce power dissipation in embedded systems. In this paper we investigate the problem of considering DVS-processing element (DVS-PE) power variations dependent on the executed tasks, during the synthesis of distributed embedded systems, and its impact on the energy savings. Unlike previous approaches, which minimise the energy consumption by exploiting the available slack time without considering the PE power profiles, a new and fast heuristic for the voltage scaling problem is proposed, which improves the voltage selection for each task dependent on the individual power dissipation caused by that task. Experimental results show that energy reductions with up to 80.7% were achieved by integrating the proposed DVS algorithm, which considers the PE power profiles, into the co-synthesis of distributed systems.

Accurate Supercapacitor Modeling for Energy Harvesting Wireless Sensor Nodes

Supercapacitors are often used in energy harvesting wireless sensor nodes (EH-WSNs) to store harvested energy. Until now, research into the use of supercapacitors in EH-WSNs has considered them to be ideal or oversimplified, with non-ideal behavior attributed to substantial leakage currents. In this brief, we show that observations previously attributed to leakage are predominantly due to redistribution of charge inside the supercapacitor. We confirm this hypothesis through the development of a circuit-based model, which accurately represents non-ideal behavior. The model correlates well with practical validations representing the operation of an EH-WSN and allows behavior to be simulated over long periods.

Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems

Dynamic voltage scaling and adaptive body biasing have been shown to reduce dynamic and leakage power consumption effectively. In this paper, we optimally solve the combined supply voltage and body bias selection problem for multi-processor systems with imposed time constraints, explicitly taking into account the transition overheads implied by changing voltage levels. Both energy and time overheads are considered. We investigate the continuous voltage scaling as well as its discrete counterpart, and we prove NP-hardness in the discrete case. Furthermore, the continuous voltage scaling problem is formulated and solved using nonlinear programming with polynomial time complexity, while for the discrete problem we use mixed integer linear programming. Extensive experiments, conducted on several benchmarks and a real-life example, are used to validate the approaches.

Improving routing efficiency for network-on-chip through contention-aware input selection

The performance of network-on-chip (NoC) largely depends on the underlying routing techniques, which have two constituencies: output selection and input selection. Previous research on routing techniques for NoC has focused on the improvement of output selection. This paper investigates the impact of input selection, and presents a novel contention-aware input selection (CAIS) technique for NoC that improves the routing efficiency. When there are contentions of multiple input channels competing for the same output channel, CAIS decides which input channel obtains the access depending on the contention level of the upstream switches, which in turn removes possible network congestion. Simulation results with different synthetic and real-life traffic patterns show that, when combined with either deterministic or adaptive output selection, CAIS achieves significant better performance than the traditional first-come-first-served (FCFS) input selection, with low hardware overhead (<3%)

A survey of multi-source energy harvesting systems

Energy harvesting allows low-power embedded devices to be powered from naturally-ocurring or unwanted environmental energy (e.g. light, vibration, or temperature difference). While a number of systems incorporating energy harvesters are now available commercially, they are specific to certain types of energy source. Energy availability can be a temporal as well as spatial effect. To address this issue, ‘hybrid’ energy harvesting systems combine multiple harvesters on the same platform, but the design of these systems is not straight-forward. This paper surveys their design, including trade-offs affecting their efficiency, applicability, and ease of deployment. This survey, and the taxonomy of multi-source energy harvesting systems that it presents, will be of benefit to designers of future systems. Furthermore, we identify and comment upon the current and future research directions in this field.

Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems

Recently, the tradeoff between energy consumption and fault-tolerance in real-time systems has been highlighted. These works have focused on dynamic voltage scaling (DVS) to reduce dynamic energy dissipation and on-time redundancy to achieve transient-fault tolerance. While the time redundancy technique exploits the available slack-time to increase the fault-tolerance by performing recovery executions, DVS exploits slack-time to save energy. Therefore, we believe there is a resource conflict between the time-redundancy technique and DVS. The first aim of this paper is to propose the use of information redundancy to solve this problem. We demonstrate through analytical and experimental studies that it is possible to achieve both higher transient fault-tolerance [tolerance to single event upsets (SEUs)] and less energy using a combination of information and time redundancy when compared with using time redundancy alone. The second aim of this paper is to analyze the interplay of transient-fault tolerance (SEU-tolerance) and adaptive body biasing (ABB) used to reduce static leakage energy, which has not been addressed in previous studies. We show that the same technique (i.e., the combination of time and information redundancy) is applicable to ABB-enabled systems and provides more advantages than time redundancy alone.

Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems

A key challenge to the future of energy-harvesting systems is the discontinuous power supply that is often generated. We propose a new approach, Hibernus, which enables computation to be sustained during intermittent supply. The approach has a low energy and time overhead which is achieved by reactively hibernating: saving system state only once, when power is about to be lost, and then sleeping until the supply recovers. We validate the approach experimentally on a processor with FRAM nonvolatile memory, allowing it to reactively hibernate using only energy stored in its decoupling capacitance. When compared to a recently proposed technique, the approach reduces processor time and energy overheads by 76%-100% and 49%-79% respectively.

Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks

High reliability against noise, high performance, and low energy consumption are key objectives in the design of on-chip networks. Recently some researchers have considered the impact of various error-control schemes on these objectives and on the tradeoff between them. In all these works performance and reliability are measured separately. However, we will argue in this paper that the use of error-control schemes in on-chip networks results in degradable systems, hence, performance and reliability must be measured jointly using a unified measure, i.e., performability. Based on the traditional concept of performability, we provide a definition for the ¿Interconnect Performability¿. Analytical models are developed for interconnect performability and expected energy consumption. A detailed comparative analysis of the error-control schemes using the performability analytical models and SPICE simulations is provided taking into consideration voltage swing variations (used to reduce interconnect energy consumption) and variations in wire length. Furthermore, the impact of noise power and time constraint on the effectiveness of error-control schemes are analyzed.