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Dive into the research topics where Paul Wai Kie Poon is active.

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Featured researches published by Paul Wai Kie Poon.


Design and process integration for microelectronic manufacturing. Conference | 2006

RET for the wiring layer of a 3D memory

Yung-Tin Chen; Paul Wai Kie Poon; Chris Petti; Vishnu Kamat; Apo Sezginer; Hsu-Ting Huang

A typical wiring layer of SanDisk 3-dimensional memory device includes a dense array of lines. Every other line terminates in an enlarged contact pad at the edge of the array. The pitch of the pads is twice the pitch of the dense array. When process conditions are optimized for the dense array, the gap between the pads becomes a weak point. The gap has a smaller depth of focus. As defocus increases, the space between the pads diminishes and bridges. We present a method of significantly increasing the depth of focus of the pads at the end of the dense array. By placing sub-resolution cutouts in the pads, we equalize the dominant pitch of the pads and the dense array.


Archive | 2008

Pillar devices and methods of making thereof

Vance Dunton; S. Brad Herner; Paul Wai Kie Poon; Chuanbin Pan; Michael Chan; Michael W. Konevecki; Usha Raghuram


Archive | 2010

Three Dimensional Horizontal Diode Non-Volatile Memory Array and Method of Making Thereof

Natalie Nguyen; Paul Wai Kie Poon; Steven J. Radigan; Michael W. Konevecki; Raghuveer S. Makala


Archive | 2011

Patterning method for high density pillar structures

Natalie Nguyen; Paul Wai Kie Poon; Steven J. Radigan; Michael W. Konevecki; Yung-Tin Chen; Raghuveer S. Makala; Vance Dunton


Archive | 2010

IMAGING POST STRUCTURES USING X AND Y DIPOLE OPTICS AND A SINGLE MASK

Yung-Tin Chen; Steven J. Radigan; Paul Wai Kie Poon; Michael W. Konevecki


Archive | 2014

Semiconductor test structures

Calvin K. Li; Yung-Tin Chen; En-Hsing Chen; Paul Wai Kie Poon


Archive | 2007

Method for reducing pillar structure dimensions of a semiconductor device

Yung-Tin Chen; Michael Chan; Paul Wai Kie Poon; Steven J. Radigan


Archive | 2007

MASK REUSE IN SEMICONDUCTOR PROCESSING

Calvin K. Li; Yung-Tin Chen; En-Hsing Chen; Paul Wai Kie Poon


Archive | 2007

TEST STRUCTURE FORMATION IN SEMICONDUCTOR PROCESSING

Calvin K. Li; Yung-Tin Chen; En-Hsing Chen; Paul Wai Kie Poon


Archive | 2011

Procédé de formation de motifs pour structures de piliers haute densité

Natalie Nguyen; Paul Wai Kie Poon; Steven J. Radigan; Michael W. Konevecki; Yung-Tin Chen; Raghuveer S. Makala; Vance Dunton

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