Paul Wielage

Networks on Silicon: Combining Best-Effort and Guaranteed Services

We advocate a network on silicon (NOS) as a hardware architecture to implement communication between IP cores in future technologies, and as a software model in the form of a protocol stack to structure the programming of NOSs. We claim guaranteed services are essential. In the ETHEREAL NOS they pervade the NOS as a requirement for hardware design, and as foundation for software programming.

XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis

Xetal-II is a SIMD processor with 320 processing elements delivering a peak performance of 107 GOPS on 16b data while dissipating 600mW. A 10Mb on-chip memory can store up to 4 VGA frames allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3Tb/s to sustain the peak-performance. The 74mm2 IC is fabricated in 90nm CMOS.

An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration

In this paper we present a network interface for an on-chip network. Our network interface decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP and DTL. Our network interface has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via network interface ports using the network itself, instead of a separate control interconnect. An example instance of this network interface with 4 ports has an area of 0.143 mm/sup 2/ in a 0.13 /spl mu/m technology, and runs at 500 MHz.

Guaranteeing the quality of services in networks on chip

Users expect a predictable quality of service (QOS) of embedded systems, even for future, more dynamic, applications. System-on-chip designers use networks on chip (NOC) to solve deep submicron problems, and to divide global problems into local, decoupled problems. NOCs provide services through protocol stacks, and introducing guaranteed services enables IP re-use and platform-based design. It also provides globally predictable behaviour, as required by the user, when combining local, decoupled solutions. There are several levels of QOS commitment (correctness, completion, completion bounds), with increasing cost. A combination of guaranteed and best-effort (no commitment) services combines their respective attractive features: predictable behaviour, and good average resource utilisation. The AETHEREAL NOC is an example of this approach, and forms the basis of a QOS-based design style, as advocated in this chapter.

Networks on silicon: blessing or nightmare?

Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those problems are encountered particularly on long wires for global interconnect. As clock frequencies increase, scaled wires become relatively slower and on-chip communication will be the limiting performance factor of future chips. We explain why efficiently sharing of the wires for long distance communication is the solution to this problem. We introduce networks on silicon (NoS), that route packets over shared (semi)-global wires. NoS performance is expected to be high, but comes at a cost. Balancing the performance and cost of a NoS is a major challenge, and we believe busses still have a role to play.

Xetal: a low-power high-performance smart camera processor

Xetal is a digital signal processor to be combined with a 30 frames per second VGA-format CMOS or CCD image sensor or any other source of digital video data. The processor is fully programmable and therefore able to run a variety of algorithms ranging from image communication to machine vision. Xetal comprises a parallel processor array and a special purpose controller to achieve high computational performances (up to 5 GOPS) with a very modest power consumption. This can go down to 30 mW for simple applications such as a digital camera for video conferencing. The Xetal chip has been realized in a 0.18 /spl mu/m CMOS process and takes up an area of 25 mm/sup 2/.

Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis

Xetal-II is a single-instruction multiple-data (SIMD) processor with 320 processing elements. It delivers a peak performance of 107 GOPS on 16-bit data while dissipating 600 mW. A 10 Mbit on-chip memory is provided which can store up to four VGA frames, allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3 Tbit/s to sustain the peak performance. The IC is realized in 90 nm CMOS and takes up 74 mm2.

Design and DfT of a high-speed area-efficient embedded asynchronous FIFO

Embedded first-in first-out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded ripple-through FIFO module with asynchronous read and write clocks. The implementation is based on a micropipeline architecture and is at least a factor two smaller than SRAM-based and standard-cell-based counterparts. This paper gives an overview of the most important design features of the new FIFO module and describes its test and design-for-test approach

Test quality analysis and improvement for an embedded asynchronous FIFO

Embedded first-in first-out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded FIFO module with asynchronous read and write clocks, which is at least a factor two smaller and also faster than SRAM-based and standard-cell-based counterparts. The detection qualities of the FIFO test for both hard and weak resistive shorts and opens have been analyzed by an IFA-like method based on analog simulation. The defect coverage of the initial FIFO test for shorts in the bit-cell matrix has been improved by inclusion of an additional data background and low-voltage testing; for low-resistant shorts, 100% defect coverage is obtained. The defect coverage for opens has been improved by a new test procedure which includes waiting periods

Service-based design of systems on chip and networks on chip

We discuss why performance verification of systems on chip (soc) is difficult, by means of an example. We identify four reasons why building socs with predictable performance is difficult: unpredictable resource usage, variable resource performance, resource sharing, and interdependent resources. We then introduce the concept of a service, aiming to address these problems, and describe its advantages over “ad-hoc” approaches. Finally, we introduce the AEthereal network on chip (noc) as a concrete example of a communication resource that implements multiple service levels.