Anteneh A. Abbo

XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis

Xetal-II is a SIMD processor with 320 processing elements delivering a peak performance of 107 GOPS on 16b data while dissipating 600mW. A 10Mb on-chip memory can store up to 4 VGA frames allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3Tb/s to sustain the peak-performance. The 74mm2 IC is fabricated in 90nm CMOS.

Camera Mote with a High-Performance Parallel Processor for Real-Time Frame-Based Video Processing

This paper describes a new smart camera mote with a high performance SIMD (single-instruction multiple-data) processor. Previous versions of our camera mote were equipped with IC3D, a line-based processor. The mote described in this paper is equipped with Xetal-II, a processor designed for frame-based real-time video analysis. The processor uses 320 processing elements in parallel to achieve performance figures of more than 100GOPS with a power consumption of 600 mWatt at peak performance. The IC has a 10Mbit internal memory cache to store and work on 4 VGA frames. The internal bandwidth to this memory is more than 1.5 Tbit/s allowing multiple passes over the images within frametime. Augmented with hardware tools for object processing, the new mote opens the door for embedded active vision applications and other iterative techniques such as watershedding and distance transforms in collaborative camera networks.

Xetal: a low-power high-performance smart camera processor

Xetal is a digital signal processor to be combined with a 30 frames per second VGA-format CMOS or CCD image sensor or any other source of digital video data. The processor is fully programmable and therefore able to run a variety of algorithms ranging from image communication to machine vision. Xetal comprises a parallel processor array and a special purpose controller to achieve high computational performances (up to 5 GOPS) with a very modest power consumption. This can go down to 30 mW for simple applications such as a digital camera for video conferencing. The Xetal chip has been realized in a 0.18 /spl mu/m CMOS process and takes up an area of 25 mm/sup 2/.

Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis

Xetal-II is a single-instruction multiple-data (SIMD) processor with 320 processing elements. It delivers a peak performance of 107 GOPS on 16-bit data while dissipating 600 mW. A 10 Mbit on-chip memory is provided which can store up to four VGA frames, allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3 Tbit/s to sustain the peak performance. The IC is realized in 90 nm CMOS and takes up 74 mm2.

Camera mote with a high-performance parallel processor for real-time frame-based video processing

This paper describes a new smart camera mote with a high performance SIMD (single-instruction multiple-data) processor. Previous versions of our camera mote were equipped with IC3D, a line-based processor. The mote described in this paper is equipped with Xetal-II, a processor designed for frame-based real-time video analysis. The processor uses 320 processing elements in parallel to achieve performance figures of more than 100 GOPS with a power consumption of 600 mWatt at peak performance. The IC has a 10 Mbit internal memory cache to store and work on 4 VGA frames. The internal bandwidth to this memory is more than 1.5 Tbit/s allowing multiple passes over the images within frametime. Augmented with hardware tools for object processing, the new mote opens the door for embedded active vision applications and other iterative techniques such as watershedding and distance transforms in collaborative camera networks.

Ultra Low Power programmable biomedical SoC for on-body ECG and EEG processing

An Ultra Low Power (ULP) biomédical System-on-Chip (SoC) has been developed for efficient ECG/EEG signal processing in a Body Area Network environment. This experimental SoC explores the use of event-driven peripheral modules that autonomously interact with external sensors together with the use of an Application-Specific-Instruction-set-Processor (ASIP) to optimize energy-efficiency during active and sleep periods. The SoC has been manufactured in standard 90nm CMOS process and use has been made of power gating to reduce leakage power that starts to become more dominant in advanced technologies. When running an ECG algorithm that is capable of reliably detecting the QRS complex in an ambulatory environment, an average power consumption of 10 μW has been measured at 0.7 V supply.

From Xetal-II to Xetal-Pro: On the Road Toward an Ultralow-Energy and High-Throughput SIMD Processor

Looking forward to the next generation of mobile streaming computing, the demanded energy efficiency of end-user terminals will become ever stringent. The Xetal-Pro processor, which is the latest member of the Xetal low-power single-instruction multiple data (SIMD) processor family from Philips, is presented in this paper. The predecessor of Xetal-Pro, known as Xetal-II, already ranks as one of the most computational-efficient [in terms of giga operations per second (GOPS)/Watt] processors available today, however, it cannot yet achieve the demanded energy efficiency (less than 1 pJ per operation). Unlike Xetal-II, Xetal-Pro supports ultrawide supply voltage (Vdd) scaling from the nominal supply to the subthreshold region. Although aggressive Vdd scaling causes severe throughput degradation, this can be partly compensated for by the massive parallelism in the Xetal family. Xetal-II includes a large on-chip frame memory (FM), which cannot be scaled well to an ultralow Vdd hence creating a big obstacle to increase energy efficiency. Therefore, we investigate both different FM realizations and memory organization alternatives. A hybrid memory system (HMS), which reduces the non-local memory traffic and enables further Vdd scaling, is proposed. For design space exploration of the right number of the scratchpad memory (SM) entries, the corresponding data locality analysis is provided, too. Moreover, some unique circuit implementation issues of Xetal-Pro such as the customized level-shifter are also discussed. Compared to Xetal-II operating at the nominal voltage, Xetal-Pro provides up to two times energy efficiency improvement even without Vdd scaling (essentially a consequence of data localization in the SM) when delivering the same amount of ultrahigh throughput. With Vdd scaling into the sub/near threshold region, Xetal-Pro could gain more than ten times energy reduction while still delivering a high throughput of 0.69 GOPS (counting multiply and add operations only). The new insight of Xetal-Pro sheds light on the direction of future ultralow-energy SIMD processors.

Mapping facial expression recognition algorithms on a low-power smart camera

Recent developments in the field of facial expression recognition advocate the use of feature vectors based on local binary patterns (LBP). Research on the algorithmic side addresses robustness issues when dealing with non-ideal illumination conditions. In this paper, we address the challenges related to mapping these algorithms on smart camera platforms. Algorithmic partitioning taking into account the camera architecture is investigated with a primary focus of keeping the power consumption low. Experimental results show that compute-intensive feature extraction tasks can be mapped on a massively-parallel processor with reasonable processor utilization. Although the final feature classification phase could also benefit from parallel processing, mapping on a general purpose sequential processor would suffice.

Power Consumption of Performance-Scaled SIMD Processors

Single-Instruction Multiple-Data (SIMD) processing is valuable in numerous compute intensive application areas, especially in pixel processing on programmable processors. With SIMD, the nice thing is that the actual hardware can be scaled to the performance and the power consumption demands of the application domain, while the software suite remains equal. In this paper, we discuss the effect of scaling on power consumption, cost and performance which is related to the characteristics of applications ranging from mobile to medical video processing. Our analysis is based on experience obtained with the Philips Xetal SIMD processor [1,2].

Scalable IC platform for smart cameras

Smart cameras are among the emerging new fields of electronics. The points of interest are in the application areas, software and IC development. In order to reduce cost, it is worthwhile to invest in a single architecture that can be scaled for the various application areas in performance (and resulting power consumption). In this paper, we show that the combination of an SIMD (single-instruction multiple-data) processor and a general-purpose DSP is very advantageous for the image processing tasks encountered in smart cameras. While the SIMD processor gives the very high performance necessary by exploiting the inherent data parallelism found in the pixel crunching part of the algorithms, the DSP offers a friendly approach to the more complex tasks. The paper continues to motivate that SIMD processors have very convenient scaling properties in silicon, making the complete, SIMD-DSP architecture suitable for different application areas without changing the software suite. Analysis of the changes in power consumption due to scaling shows that for typical image processing tasks, it is beneficial to scale the SIMD processor to use the maximum level of parallelism available in the algorithm if the IC supply voltage can be lowered. If silicon cost is of importance, the parallelism of the processor should be scaled to just reach the desired performance given the speed of the silicon.