Paul Zuber

Atomistic approach to variability of bias-temperature instability in circuit simulations

A blueprint for an atomistic approach to introducing time-dependent variability into a circuit simulator in a realistic manner is demonstrated. The approach is based on previously proven physics of stochastic properties of individual gate oxide defects and their impact on FET operation. The proposed framework is capable of following defects with widely distributed time scales (from fast to quasi-permanent), thus seamlessly integrating random telegraph noise (RTN) effects with bias temperature instability (BTI). The use of industry-standard circuit simulation tools allows for studying realistic workloads and the interplay of degradation of multiple FETs.

Variability aware modeling of SoCs: From device variations to manufactured system yield

As CMOS technology feature sizes decrease, random within-die and inter-die process variations more and more jeopardize SoC parametric and functional yield. Largely neglected in the State-Of-the-Art, dynamic energy consumption and power dissipation becomes heavily affected. This paper describes a technique to systematically bring statistically correlated timing/energy variations all the way up from the device to the SoC level. We propose a flow for Variability Aware Modeling (VAM) and apply it to a case study using a industrial test vehicle.

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes

This paper proposes TEASE (Technology Exploration and Analysis for SoC-level Evaluation), a framework to systematically analyze and evaluate system design in finFET-based technology node. The proposed framework combines both lithography and electrical constraints of a particular technology node to optimize the standard cell library performance. Growing complexity of logic design at nodes below 20nm causes to adopt a design style that can embrace the simplicity required to enable manufacturing, along with a process technology that can be finely tuned to the desired performance constraints. Additionally, the introduction of finFET based devices poses a new challenge for the designers to come up with an efficient standard cell template. The proposed framework can be used to detect the technology constraints that act as the bottleneck for the enablement of design at these advanced nodes. Results presented in this paper show by optimizing these bottlenecks we can improve the performance of a standard cell library significantly. Furthermore, adapting to such an analysis framework at an early stage of technology development helps to take the design constraints into the decision loop for realization of technology research into real products.

A holistic approach for statistical SRAM analysis

We present a new method and its implementation that enables design-phase assessment of statistical performance metrics of semiconductor memories under random local and global process variations. Engineers use the tool to reduce design margins and to maximize parametric yield. Results on industry grade 45nm SRAM designs show that this holistic approach is significantly more accurate than the alternatives based on global corners or critical path netlist, which can lead to unexpected yield loss.

Impact of fin height variations on SRAM yield

We demonstrate that the variation of threshold voltage Vt of bulk finFET (BFF) devices due to the fin height variation (FHV) constitutes the major part of the overall device variations. Yet, the inter-die FHV affects SRAM cell variation performance in quantitatively comparable manner to intra-die variations (or mismatch). At the product level, however the impact of that component on array performance is negligible, demonstrating that mismatch remains dominating the overall statistical SRAM response and upper yield limit.

New reliability mechanisms in memory design for sub-22nm technologies

The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells, and what kind of circuit solution would be required to maintain the current yield level. Later, we discuss the impact of errors at the system level, and different approaches at system level to adapt the heterogeneous systems to users requirements.

Circuit-design oriented modelling of the recovery BTI component and post-BD gate currents

In ultra-scaled technologies, the absence of suitable models for the MOSFET aging mechanisms leads to a lack of understanding of their real impact on the circuit performance and reliability. In this work, models for two of the main reliability issues at device level, Bias Temperature Instability (BTI) and time dependent dielectric breakdown (TDDB), are presented. The models cover important properties of both phenomena, such as the threshold voltage recovery for BTI or the transistor area and voltage dependences for TDDB. Both models, which can be easily implemented in circuit simulators, have been used to study the BTI and TDDB impact in invertors and current mirrors performance, respectively.

Analysis of FinFET technology on memories

Summary form only given. Due to increased leakage currents and variability, classical bulk technology is reaching its scaling limits and some alternatives must be found. FinFETs are one of those alternatives. Through their 3D structure, they achieve better channel control which is the key to scalability. However, some sources of variability still remain. The impact of this technology shift on SRAM and DRAM memories is analyzed in this work.

TRAMS Project: variability and reliability of SRAM memories in sub-22nm bulk-CMOS technologies

The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13 nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells and circuits.