Petr Dobrovolny

Atomistic approach to variability of bias-temperature instability in circuit simulations

A blueprint for an atomistic approach to introducing time-dependent variability into a circuit simulator in a realistic manner is demonstrated. The approach is based on previously proven physics of stochastic properties of individual gate oxide defects and their impact on FET operation. The proposed framework is capable of following defects with widely distributed time scales (from fast to quasi-permanent), thus seamlessly integrating random telegraph noise (RTN) effects with bias temperature instability (BTI). The use of industry-standard circuit simulation tools allows for studying realistic workloads and the interplay of degradation of multiple FETs.

Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits

The design of analog front-ends of digital telecommunication transceivers requires mixed-signal simulations at the architectural level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the architectural level, especially when the nonlinear behavior is frequency dependent. This paper describes an analysis and modeling method based on Volterra theory. The method derives bottom-up models of nonlinear analog continuous-time circuits. These behavioral models predict the dominant nonlinear effects using a composition of linear transfer functions and multiplications. This makes it possible to accurately model frequency dependencies and to gain insight into the dominant nonlinear sources of the circuit. The basic models are afterwards described using its multicarrier complex low-pass representation to enable their efficient cosimulation with the digital circuits in a dataflow simulation environment. The multicarrier representation is a direct extension of the classically used complex low-pass equivalent models, which considers the modulation of a single carrier only. The accuracy of the multicarrier representation is higher than classical complex low-pass equivalent models since out-of-band nonlinear distortion is taken into account. The main advantage of the proposed technique is that it yields both insight in the nonlinear behavior at the circuit level and that it provides an important gain in simulation efficiency of RF integrated circuits at the system level. Both aspects are demonstrated on a 5-GHz WLAN design.

A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers

The explosion of the telecommunications market requires miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. New architectures must therefore be simulated at high level. Current methodologies and corresponding tools suffer from common drawbacks, such as lower accuracy, slow simulation speed, etc. A new methodology has been developped for the efficient simulation, at the architectural level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a multi-rate, multi-carrier signal representation together with a dataflow simulation scheme which switches dynamically towards the most efficient signal processing technique available. An implementation of this methodology shows both excellent runtimes and a high accuracy.

Propagating variability from technology to system level

As CMOS technology feature sizes decrease, variability more and more jeopardizes system level parametric and functional yield. This paper proposes a framework that can capture variability at all levels in the design flow. It offers a correlated view on yield, timing, dynamic and static energy. Preservation on rare events in variability distributions is obtained by the Weighted Monte Carlo technique.

A holistic approach for statistical SRAM analysis

We present a new method and its implementation that enables design-phase assessment of statistical performance metrics of semiconductor memories under random local and global process variations. Engineers use the tool to reduce design margins and to maximize parametric yield. Results on industry grade 45nm SRAM designs show that this holistic approach is significantly more accurate than the alternatives based on global corners or critical path netlist, which can lead to unexpected yield loss.

Impact of fin height variations on SRAM yield

We demonstrate that the variation of threshold voltage Vt of bulk finFET (BFF) devices due to the fin height variation (FHV) constitutes the major part of the overall device variations. Yet, the inter-die FHV affects SRAM cell variation performance in quantitatively comparable manner to intra-die variations (or mismatch). At the product level, however the impact of that component on array performance is negligible, demonstrating that mismatch remains dominating the overall statistical SRAM response and upper yield limit.

Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits

The architectural study of wireless communication systems typically requires simulations with high-level models for different analog and RF blocks. Among these blocks, frequency-translating devices such as mixers pose problems in RF circuit simulation since their response typically covers a mix of long- and short-time scales. This paper proposes a technique to analyze and model nonlinear frequency-translating RF circuits such as up- and downconversion mixers. The proposed method is based on a generalized Volterra series approach for periodically time-varying systems. It enables a multi-tone distortion analysis starting from a circuit description and derives simplified high-level models based on the most important nonlinear contributions. These models give both insight in the nonlinear behavior and enable an efficient high-level simulation during architectural design of front-ends of RF transceivers.

Generation of multicarrier complex lowpass models of RF ICs

The design of transceivers for wireless digital telecommunications is subject to severe requirements on cost and power consumption. This is a challenge for the design of RF front-end blocks that degrade the bit-error-rate of a telecommunication link. This paper describes a technique to generate accurate high-level models for the RF front-end blocks. The models take into account the nonlinear behavior as a function of frequency. The accuracy of the models is higher than classical complex equivalent models since out-of-band distortion is taken into account. The technique, that is verified with a low-noise amplifier design for 5 GHz WLAN, yields an important gain in simulation efficiency of RF ICs, compared to circuit-level simulations.

Systematic stability-analysis method for analog circuits

Analyzing the stability of an analog circuit is an important part of the circuit design. Several commercial simulators are equipped with special stability analysis techniques. Problems arise when your design kit does not support such simulator. Another issue is when the designer wants to get insight into the sources of the instability to propose a stabilization. This can be done through analyzing the open-loop or the closed-loop transfer function of the circuit. The aim of this paper is to propose an automated analysis method which identifies the nodes to be considered for stabilization. The method does not need to break feedback loops or to manipulate netlists. It only uses AC simulations and does not require the full modified nodal equations. The method is illustrated on 3 design examples: a voltage controlled oscillator (VCO), a reference bias circuit and the common-mode feedback network in a gm-C filter