Pauline C. Haddow

Bridging the genotype-phenotype mapping for digital FPGAs

To solve the genome complexity issue and enable evolution of large complex circuits, the need to move away from a one-to-one genotype/phenotype mapping is becoming generally accepted. This involves development of new forms of representation with features such as growth. Shrinking the size of the genotype in effect moves complexity from the genotype representation to the genotype/phenotype mapping. The field of digital evolvable hardware is relatively young but already researchers have not only had to move through different technology platforms i.e. 6200, 4000 and Virtex series, but also evolution friendly features have disappeared. A mass produced evolution friendly reconfigurable platform is not likely to be ahead of us and a newer technology more evolution friendly than traditional reconfigurable platforms is not around the corner. To be able to reuse results and lessons learned from todays technology on tomorrows technology and exploit the power of evolution, one solution is to provide a virtual evolution friendly reconfigurable platform which may be mapped onto a given technology. We propose a two stage genotype/phenotype mapping using our virtual evolvable hardware FPGA us the bridge. The two stages simplify the genotype/phenotype transition at the same time as the virtual evolvable hardware FPGA bridge provides a more evolution friendly platform, further reducing the complexity of the genotype representation.

Shrinking the Genotype: L-systems for EHW?

Inspired by biological development where from a single cell, a complex organism can evolve, we are interested in finding ways in which artificial development may be introduced to genetic algorithms so as to solve our genotype challenge. This challenge may be expressed in terms of shrinking the genotype. We need to move away from a oneto-one genotype-phenotype mapping so as to enable evolution to evolve large complex electronic circuits. We present a first case study where we have considered the mathematical formalism L-systems and applied their principles to the development of digital circuits. Initial results, based on extrinsic evolution, indicate that our representation based on L-systems provides an interesting methodology for further investigation. We also present our implementation platform for intrinsic evolution with development, enabling on-chip evaluation of grown solutions.

Prototyping a GA Pipeline for complete hardware evolution

In this paper a new approach to evolvable hardware is introduced termed Complete Hardware Evolution (CHE). This method differs from Extrinsic and Intrinsic evolution in that the evolution process itself is implemented in hardware. In addition, the evolution process implementation, referred to herein as the GA Pipeline, is implemented on the same chip as the evolving design. A prototype implementation of the GA Pipeline is presented which uses FPGA technology as the implementation medium.

An evolvable hardware FPGA for adaptive hardware

Can we realise the opportunities that lie in design by evolution by using traditional technologies or are there better technologies which will allow us to fully realise the potential inherent in evolvable hardware? The authors consider the characteristics of evolvable hardware, especially for adaptive design, and discuss the demands that these characteristics place on the underlying technology. They suggest a potential alternative to todays FPGA technology. The proposed architecture is particularly focused at reducing the genotype required for a given design by reducing the configuration data required for unused routing resources and allowing partial configuration down to a single CLB. In addition, to support adaptive hardware, self-reconfiguration is enabled.

Challenges of evolvable hardware: past, present and the path to a promising future

Nature is phenomenal. The achievements in, for example, evolution are everywhere to be seen: complexity, resilience, inventive solutions and beauty. Evolvable Hardware (EH) is a field of evolutionary computation (EC) that focuses on the embodiment of evolution in a physical media. If EH could achieve even a small step in natural evolution’s achievements, it would be a significant step for hardware designers. Before the field of EH began, EC had already shown artificial evolution to be a highly competitive problem solver. EH thus started off as a new and exciting field with much promise. It seemed only a matter of time before researchers would find ways to convert such techniques into hardware problem solvers and further refine the techniques to achieve systems that were competitive with or better than human designs. However, 15xa0years on—it appears that problems solved by EH are only of the size and complexity of that achievable in EC 15xa0years ago and seldom compete with traditional designs. A critical review of the field is presented. Whilst highlighting some of the successes, it also considers why the field is far from reaching these goals. The paper further redefines the field and speculates where the field should go in the next 10xa0years.

Towards Development on a Silicon-based Cellular Computing Machine

Today’s reconfigurable technology provides vast parallelism that may be exploited in the design of a cellular computing machine (CCM). In this work a virtual Sblock FPGA is implemented on an existing FPGA, achieving not only an architecture in keeping with cellular computing principles but also suited to biologically inspired design methods. The design method proposed is a combination of evolution and development and results of running a developmental model on the CCM are presented.

Evolving an adaptive digital filter

One important feature of signal processing is coping with noise. In a non-adaptive filter, characteristics of the filter may be refined to remove noise. One method of achieving this is to use evolution to decide the filter characteristics. However, if the noise level is sufficient or the input signal is not of the required type for the output signal required, then a satisfactory output signal may not be achievable. To be able to achieve the required output signal for a wide range of input signals and noise, it is desirable to be able to adjust both the characteristics and the type of the filter. In this way the resulting filter may be said to be an adaptive filter. In this paper we propose an on-chip solution for an adaptive digital filter using an on-chip evolvable hardware method. We highlight a challenge within evolvable hardware for adaptive designs and that is to find efficient ways in which sufficient genetic material will be available to the evolution process. This problem appears when the evolution process is automatically restarted so as to adapt to a change in the environment.

Developmental mappings and phenotypic complexity

The effect of phenotypic complexity on distance correlation plots is investigated for two developmental mappings, a mapping based on L-systems, and a 2D cellular automata mapping. Our treatment of complexity is based on the theory of Kolmogorov complexity. A new genotype sampling algorithm called cross section walk is introduced.

Biologically-Inspired: A Rule-Based Self-Reconfiguration of a Virtex Chip

To be able to evolve digital circuits with complex structure and/or complex functionality we propose an artificial development process as the genotype-phenotype mapping. To realistically evolve such circuits a hardware implementation of the development process together with high-speed reconfiguration logic for phenotype implementation is presented. The hardware implementation of the development process is a programmable reconfiguration processor. The high-speed reconfiguration logic for evaluation of the phenotype is capable of exploiting the advantage of massive parallel processing due to the cellular automata like structure.

Building knowledge into developmental rules for circuit design

Inspired by biological development, we wish to introduce a circuit-DNA that may be developed to a given circuit design organism. This organism is a member of a Virtual EHW FPGA species that may be mapped onto a physical FPGA. A rule-based circuit-DNA, as used herein, provides a challenge to find suitable rules for artificial development of such an organism. Approaching this challenge, the work herein may be said to be of an investigative nature, to explore for developmental rules for developing even the simplest organism. n nThe artificial developmental process introduced herein, uses a knowledge rich representation including both knowledge of the circuits (organisms) building blocks and local knowledge about neighbouring cells. Initial experiments for knowledge rich development on our virtual technology platform, are presented.