Paulo Matias

Individual discrimination of freely swimming pulse-type electric fish from electrode array recordings

Abstract Pulse-type weakly electric fishes communicate through electrical discharges with a stereotyped waveform, varying solely the interval between pulses according to the information being transmitted. This simple codification mechanism is similar to the one found in various known neuronal circuits, which renders these animals as good models for the study of natural communication systems, allowing experiments involving behavioral and neuroethological aspects. Performing analysis of data collected from more than one freely swimming fish is a challenge since the detected electric organ discharge (EOD) patterns are dependent on each animal׳s position and orientation relative to the electrodes. However, since each fish emits a characteristic EOD waveform, computational tools can be employed to match each EOD to the respective fish. In this paper we describe a computational method able to recognize fish EODs from dyads using normalized feature vectors obtained by applying Fourier and dual-tree complex wavelet packet transforms. We employ support vector machines as classifiers, and a continuity constraint algorithm allows us to solve issues caused by overlapping EODs and signal saturation. Extensive validation procedures with Gymnotus sp. showed that EODs can be assigned correctly to each fish with only two errors per million discharges.

An embedded system for real-time feedback neuroscience experiments

A complete data acquisition and signal output control system for synchronous stimuli generation, geared towards in vivo neuroscience experiments, was developed using the Terasic DE2i-150 board. All emotions and thoughts are an emergent property of the chemical and electrical activity of neurons. Most of these cells are regarded as excitable cells (spiking neurons), which produce temporally localized electric patterns (spikes). Researchers usually consider that only the instant of occurrence (timestamp) of these spikes encodes information. Registering neural activity evoked by stimuli demands timing determinism and data storage capabilities that cannot be met without dedicated hardware and a hard real-time operational system (RTOS). Indeed, research in neuroscience usually requires dedicated electronic instrumentation for studies in neural coding, brain machine interfaces and closed loop in vivo or in vitro experiments. We developed a complete embedded system solution consisting of a hardware/software co-design with the Intel Atom processor running a free RTOS and a FPGA communicating via a PCIe-to-Avalon bridge. Our system is capable of registering input event timestamps with 1{\mu}s precision and digitally generating stimuli output in hard real-time. The whole system is controlled by a Linux-based Graphical User Interface (GUI). Collected results are simultaneously saved in a local file and broadcasted wirelessly to mobile device web-browsers in an user-friendly graphic format, enhanced by HTML5 technology. The developed system is low-cost and highly configurable, enabling various neuroscience experimental setups, while the commercial off-the-shelf systems have low availability and are less flexible to adapt to specific experimental configurations.

A Parallel Hardware Architecture based on Node-Depth Encoding to Solve Network Design Problems

Many problems involving network design can be found in the real world, such as electric power circuit planning, telecommunications and phylogenetic trees. In general, solutions for these problems are modeled as forests represented by a graph manipulating thousands or millions of input variables, making it hard to obtain the solutions in a reasonable time. To overcome this restriction, Evolutionary Algorithms (EAs) with dynamic data structures (encodings) have been widely investigated to increase the performance of EAs for Network Design Problems (NDPs). In this context, this paper proposes a parallelization of the node-depth encoding (NDE), a data structure especially designed for NDPs. Based on the NDE the authors have developed a parallel algorithm and a hardware architecture implemented on FPGA (Field-Programmable Gate Array), denominated Hardware Parallelized NDE (HP-NDE). The running times obtained in a general purpose processor (GPP) and the HP-NDE are compared. The results show a significant speedup in relation to the GPP solution, solving NDP in a time limited by a constant. Such time upper bound can be satisfied for any size of network until the hardware resources available on the FPGA are depleted. The authors evaluated the HP-NDE on a Stratix IV FPGA with networks containing up to 2048 nodes.

Exploiting Kant and Kimura’s Matrix Inversion Algorithm on FPGA

Matrix inversion for real-time applications can be a challenge for the designers since its computational complexity is typically cubic. Parallelism has been widely exploited to reduce such complexity, however most traditional methods do not scale well with the matrix size leading to communication bottlenecks. In this paper we exploit a decentralised parallel hardware architecture based on a strongly non-singular matrix inversion algorithm proposed by Kant and Kimura in 1978, which is a parallel-orientated method with communication mode independent of the matrix size, mitigating the problem of matrix scalability. The hardware architecture is implemented in two different approaches using fixed-point arithmetic: dedicated and shared. In the first approach a matrix can be inverted in linear time while the latter, for the best case, has a square complexity. Experimental results are demonstrated using a Stratix V GX FPGA. For instance, in dedicated approach an 8x8 matrix is inverted in 1.27us, while in shared approach a 64x64 matrix is inverted in 153.40us using 64 pipelined processing elements.

Automated pulse discrimination of two freely-swimming weakly electric fish and analysis of their electrical behavior during dominance contest

Electric fishes modulate their electric organ discharges with a remarkable variability. Some patterns can be easily identified, such as pulse rate changes, offs and chirps, which are often associated with important behavioral contexts, including aggression, hiding and mating. However, these behaviors are only observed when at least two fish are freely interacting. Although their electrical pulses can be easily recorded by non-invasive techniques, discriminating the emitter of each pulse is challenging when physically similar fish are allowed to freely move and interact. Here we optimized a custom-made software recently designed to identify the emitter of pulses by using automated chirp detection, adaptive threshold for pulse detection and slightly changing how the recorded signals are integrated. With these optimizations, we performed a quantitative analysis of the statistical changes throughout the dominance contest with respect to Inter Pulse Intervals, Chirps and Offs dyads of freely moving Gymnotus carapo. In all dyads, chirps were signatures of subsequent submission, even when they occurred early in the contest. Although offs were observed in both dominant and submissive fish, they were substantially more frequent in submissive individuals, in agreement with the idea from previous studies that offs are electric cues of submission. In general, after the dominance is established the submissive fish significantly changes its average pulse rate, while the pulse rate of the dominant remained unchanged. Additionally, no chirps or offs were observed when two fish were manually kept in direct physical contact, suggesting that these electric behaviors are not automatic responses to physical contact.

Low-Resource Bluespec Design of a Modular Acquisition and Stimulation System for Neuroscience (Abstract Only)

We have compared two different resource arbitration architectures in our developed data acquisition and stimuli generator system for neuroscience research, entirely specified in a high-level Hardware Description Language (HDL). One of them was designed with a decoupled and latency insensitive modular approach, allowing for easier code reuse, while the other adopted a centralized scheme, constructed specifically for our application. The usage of a high-level HDL allowed straightforward and stepwise code modifications to transform one architecture into the other. Despite the logic complexity penalty of synthesizing our hardware from a highly abstract language, both architectures were implemented in a very small programmable logic device without even consuming all the hardware resources. While the decoupled design has shown more resilience to input activity bursts, the centralized one gave an economy of about 10-15% in the device logic element usage. This system is not only useful for neuroscience protocols that require timing determinism and synchronous stimuli generation, but has also demonstrated that high-level languages can be effectively used for synthesizing hardware in small programmable devices.

Modular Acquisition and Stimulation System for Timestamp-driven Neuroscience Experiments

Dedicated systems are fundamental for neuroscience experimental protocols that require timing determinism and synchronous stimuli generation. We developed a data acquisition and stimuli generator system for neuroscience research, optimized for recording timestamps from up to 6 spiking neurons and entirely specified in a high-level Hardware Description Language (HDL). Despite the logic complexity penalty of synthesizing from such a language, it was possible to implement our design in a low-cost small reconfigurable device. Under a modular framework, we explored two different memory arbitration schemes for our system, evaluating both their logic element usage and resilience to input activity bursts. One of them was designed with a decoupled and latency insensitive approach, allowing for easier code reuse, while the other adopted a centralized scheme, constructed specifically for our application. The usage of a high-level HDL allowed straightforward and stepwise code modifications to transform one architecture into the other. The achieved modularity is very useful for rapidly prototyping novel electronic instrumentation systems tailored to scientific research.

Expanding the horizontal capabilities of CRT monitors using artificial inter-pixel steps for neuroscience experiments

This article describes the development of a visual stimulus generator to be used in neuroscience experiments with invertebrates such as flies. The experiment consists in the visualization of a fixed image that is displaced horizontally according to the stimulus data. The system is capable of displaying 640x480 pixels with 256 intensity levels at 200 frames per second (FPS) on conventional raster monitors. To double the possible horizontal positioning possibilities from 640 to 1280, a novel technique is presented introducing artificial inter-pixel steps. The implementation consists in using two video frame buffers containing each a distinct view of the desired image pattern. This implementation generates a visual effect capable of doubling the horizontal positioning capabilities of the visual stimulus generator allowing more precise and movements more contiguous.

Spanning forests in constant time using FPGAS applied to network design problems

Problems involving network design can be found in many real world applications such as power systems, vehicle routing, telecommunication networks, phylogenetic trees, among others. These problems involve thousands or millions of input variables and often need information and solution in real time. In general, they are computationally complex (NP-Hard). In this context, metaheuristics like evolutionary algorithms have been investigated. Recently, researches have shown that the performance of evolutionary algorithms for network design problems can be significantly increased by means of more appropriate dynamic data structures (encodings). To achieve high performance, we parallelized the application via a dynamic data structure, called node-depth encoding for representation of a set (population) of spanning forests. This paper proposes an FPGA-based hardware architecture, denominated Hardware-Parallelized NDE (HPNDE), which is able to generate spanning trees (forests) in a constant average running time O(1), enabling its application in real large-scale problems, given an FPGA with enough resources to implement such structure. The parallelized approach is 1.5k times faster than its sequential counterpart.