Paulo Sérgio B. Nascimento

A partial reconfigurable architecture for controllers based on Petri nets

The digital control systems in industry has been used in most of the applications based on expensive programmable logical controllers (PLC). These systems are, in general, highly complex and slow, with an operation cycle around 10 ms. In this work, a reconfigurable logic controller (RLC) approach is presented, based on a small and low cost Xilinx Virtex-II FPGA architecture, operating as a virtual hardware machine. In this context, the main process is specified in a formal language, based on Petri nets or SFC (sequential function chart). For applications that demand more hardware than that available in the FPGA, a partial reconfiguration mechanism takes place. From the Petri net specification, the main process is split into multiple contexts, which are sequentially executed within the same FPGA, without violating the operation cycle of application.

Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration

High parallelism degree is fundamental for high speed image processing systems. Modern FPGA devices can provide such parallelism plus flexibility. Temporal partitioning techniques can be used to implement large systems, splitting them into partitions (called contexts), multiplexed in a FPGA. This approach can increase the effective FPGA area, allowing high parallelism in the application tasks. However, the context reconfigurations can cause performance decrease. Intensive parallelism exploration of massive image data application compensates this overhead and can improve global performance. In this work, one reconfigurable computer platform and design space exploration techniques are proposed for mapping of image processing applications into FPGA slices. A library with different hardware implementation for different parallelism degree is used to better adjust space/time for each task. Experiments demonstrate the efficiency of the approach when compared to the optimal mapping reached by exhaustive timing search in the complete design space exploration.

A timed Petri net approach for pre-runtime scheduling in partial and dynamic reconfigurable systems

Dynamic reconfigurable systems (DRS) offer a very interesting alternative for embedded digital systems design. Tasks scheduling within a reconfigurable environment allows the development of systems with better execution performance, chip area economy and lower power consumption. This paper describes an algorithm for design of dynamically reconfigurable systems where tasks scheduling have as prime objective the overall application performance speedup. The methodology includes the generation of an embedded controller supporting the scheduling process in a target architecture.

Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA

Recently, the manufactures of supercomputers have made use of FPGAs to accelerate scientific applications [16][17]. Traditionally, the FPGAs were used only on non-scientific applications. The main reasons for this fact are: the floating-point computation complexity; the FPGA logic cells are not sufficient for the scientific cores implementation; the cores complexity prevents them to operate on high frequencies. Nowadays, the increase of specialized blocks availability in complex operations, as sum and multiplier blocks, implemented directly in FPGA and, the increase of internal RAM blocks (BRAMs) have made possible high performance systems that use FPGA as a processing element for scientific computation [2]. These devices are used as co-processors that execute intensive computation. The emphasis of these architectures is the exploration of parallelism present on scientific computation operations and data reuse. In major of these applications, the scientific computation uses, in general, operations of big floating-point dense matrices, which are normally operated by MACs. In this work, we describe the architecture of an accumulative multiplier (MAC) in double precision floating-point, according to IEEE-754 standard and we propose the architecture of a multiplier of matrices that uses developed instances of the MACs and explores the reuse of data through the use of the BRAMs (Blocks of RAM internal to the FPGAs) of a Xilinx Virtex 4 LX200 FPGA. The synthesis results showed that the implemented MAC could reach a performance of 4GFLOPs.

AN ENERGY-AWARE EXPLORATION APPROACH BASED ON OPEN SOFTWARE ENVIRONMENT

In this work it is presented an automated method for tuning memory hierarchy to embedded applications in order to reduce energy consumption. Detailed studies were performed on TCaT heuristic in order to obtain a new exploration approach. Experiments show a reduction of approximately 4 times in the energy consumption by using our heuristic, considering two-level caches. An open software environment, based on SystemC, to explore architectures aiming energy consumption on cache memory hierarchy, has been extended. MediaBench benchmark has been used.

CDFG-Petri net temporal partitioning for switching context applications

Reconfigurable computing has made promising progress. The development of platforms that match the reconfigurable hardware with programmable elements, such as DSPs or microprocessors, promise great applicability in diverse areas in the future. In this article, we describe a co-design methodology for single-context and virtual hardware applications based on Petri nets for the PISH design environment. A platform description is presented as well as the reconfiguration methodology. A temporal partitioning is described, exploring different solutions for different applications with time and communication constraints.

Aquarius: a dynamically reconfigurable computing platform

This work presents the development of a dynamically reconfigurable computing platform targeting Virtex-II devices under control of a host system based on the Nios II soft-core processor from Altera. The platform, called Aquarius, controls the system by means of the μCLinux embedded Operating System (OS). Through this OS, an IP-SelectMAP core and its device driver, a Virtex-II FPGA device can be totally or partially reconfigured. Given that the partial reconfiguration does not affect the other running areas the partial reconfiguration is dynamic. Two programs have been developed in order to validate both reconfiguration styles. This programs control the application tasks execution and their respective bitstreams, according to the tasks scheduling. The platform has been prototyped and an example has been developed and is presented in this work.

A partial reconfigurable FPGA implementation for industrial controllers using SFC-petri net description (abstract only)

Sequential Control System in the industry has been used in applications based on Programmable Logical Controllers (PLC). These Systems are, in general, highly complex and with an operation cycle around 1ms or 10ms. PLC are, in general, expensive for theses high complex applications. In this work, a Dynamical Reconfigurable approach is presented, based on Xilinx Virtex-II FPGA architecture, operating as a virtual hardware machine. In this context, the control process is specified in the industrial standard language SFC/Petri net (Sequential Function Chart). For large controllers, a partial and dynamical reconfiguration mechanism takes place and the controller is split into multiple contexts, which are sequentially executed within the same FPGA, without violating the operation cycle of the system, in spite of the reconfiguration overhead. The solution is cost compatible with current PLC for complex applications and can reach better performance by exploration of the potential parallelism of control descriptions.

A petri-net based Pre-runtime scheduler for dynamically self-reconfiguration of FPGAs (abstract only)

Dynamically Reconfigurable Systems (DRS) offer a very interesting alternative for embedded digital systems design. Tasks scheduling within a reconfigurable environment allows the development of systems with better execution performance, chip area economy and lower power consumption. This paper describes a Petri Net based methodology for the design of dynamically reconfigurable systems, where tasks scheduling has as prime objective the best temporal performance of the overall application. The methodology includes the generation of an embedded controller supporting the scheduling process in the target architecture.