Manoel Eusebio de Lima

Hyperspectral images clustering on reconfigurable hardware using the k-means algorithm

Unsupervised clustering is a powerful technique for understanding multispectral and hyperspectral images, k-means being one of the most used iterative approaches. It is a simple though computationally expensive algorithm, particularly for clustering large hyperspectral images into many categories. Software implementation presents advantages such as flexibility and low cost for implementation of complex functions. However, it presents limitations, such as difficulties in exploiting parallelism for high performance applications. In order to accelerate the k-means clustering, a hardware implementation could be used. The disadvantage in this approach is that any change in the project requires previous knowledge of the hardware design process and can take several weeks to be implemented. In order to improve the design methodology, an automatic and parameterized implementation for hyperspectral images has been developed in a hardware/software codesign approach. An unsupervised clustering technique k-means that uses the Euclidian distance to calculate the pixel to centers distance was used as a case study to validate the methodology. Two implementations, a software and a hardware/software codesign one, have been implemented. Although the hardware component operates at 40 MHz, being 12.5 times less than the software operating frequency (PC), the codesign implementation was approximately 2 times faster than software one.

A partial reconfigurable architecture for controllers based on Petri nets

The digital control systems in industry has been used in most of the applications based on expensive programmable logical controllers (PLC). These systems are, in general, highly complex and slow, with an operation cycle around 10 ms. In this work, a reconfigurable logic controller (RLC) approach is presented, based on a small and low cost Xilinx Virtex-II FPGA architecture, operating as a virtual hardware machine. In this context, the main process is specified in a formal language, based on Petri nets or SFC (sequential function chart). For applications that demand more hardware than that available in the FPGA, a partial reconfiguration mechanism takes place. From the Petri net specification, the main process is split into multiple contexts, which are sequentially executed within the same FPGA, without violating the operation cycle of application.

Heuristic for two-level cache hierarchy exploration considering energy consumption and performance

In this work is presented an automated method for adjusting two-level cache memory hierarchy in order to reduce energy consumption in embedded applications. The proposed heuristic, TECH-CYCLES (Two-level Cache Exploration Heuristicconsidering CYCLES), consists of making a small search in the space of configurations of the two-level cache hierarchy, analyzing the impact of each parameter in terms of energy and number of cycles spent for a given application. Experiments show an average reduction of about 41% in the energy consumption by using our heuristic when compared with the existing heuristic (TCaT), also for two-level caches. Besides the energy improvement, this method also reduces the number of cycles needed to execute a given application by about 25%. In order to validate the proposed heuristic, twelve benchmarks from the MiBench suite have been used.

An ESL approach for energy consumption analysis of cache memories in SoC platforms

The design of complex circuits as SoCs presents two great challenges to designers. One is the speeding up of system functionality modeling and the second is the implementation of the system in an architecture that meets performance and power consumption requirements. Thus, developing new high-level specification mechanisms for the reduction of the design effort with automatic architecture exploration is a necessity. This paper proposes an Electronic-System-Level (ESL) approach for system modeling and cache energy consumption analysis of SoCs called PCacheEnergy Analyzer. It uses as entry a high-level UML-2.0 profile model of the system and it generates a simulation model of a multicore platform that can be analyzed for cache tuning. PCacheEnergyAnalyzer performs static/dynamic energy consumption analysis of caches on platforms that may have different processors. Architecture exploration is achieved by letting designers choose different processors for platform generation and different mechanisms for cache optimization. PCacheEnergy Analyzer has been validated with several applications of Mibench, Mediabench, and PowerStone benchmarks, and results show that it provides analysis with reduced simulation effort

Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration

High parallelism degree is fundamental for high speed image processing systems. Modern FPGA devices can provide such parallelism plus flexibility. Temporal partitioning techniques can be used to implement large systems, splitting them into partitions (called contexts), multiplexed in a FPGA. This approach can increase the effective FPGA area, allowing high parallelism in the application tasks. However, the context reconfigurations can cause performance decrease. Intensive parallelism exploration of massive image data application compensates this overhead and can improve global performance. In this work, one reconfigurable computer platform and design space exploration techniques are proposed for mapping of image processing applications into FPGA slices. A library with different hardware implementation for different parallelism degree is used to better adjust space/time for each task. Experiments demonstrate the efficiency of the approach when compared to the optimal mapping reached by exhaustive timing search in the complete design space exploration.

A timed Petri net approach for pre-runtime scheduling in partial and dynamic reconfigurable systems

Dynamic reconfigurable systems (DRS) offer a very interesting alternative for embedded digital systems design. Tasks scheduling within a reconfigurable environment allows the development of systems with better execution performance, chip area economy and lower power consumption. This paper describes an algorithm for design of dynamically reconfigurable systems where tasks scheduling have as prime objective the overall application performance speedup. The methodology includes the generation of an embedded controller supporting the scheduling process in a target architecture.

A SystemC-only design methodology and the CINE-IP multimedia platform

The increasing complexity of modern System-on-Chip (SoC) platforms has revealed the need for methodologies that enable a rigorous engineering design process, based on a combination of Electronic System Level (ESL) description languages, and IP-core modeling and reuse. On the other hand, ESL modeling has faced designers with the same methodology problems encountered in the design of large computer programs. In this paper, we describe a SystemC-only IP-core design process, called IP PROCESS (IPP). IPP is inspired on two rigorous software engineering processes (RUP and XP), and on well-known hardware design standards (VSIA and RMM). The IPP Verification Methodology (IPV) is based on a careful refinement of the SystemC behavioral description towards RTL. Such approach enabled a continuous co-simulation against the behavioral reference model, while allowed for a SystemC-only environment. As a result, we have experienced a considerable reduction in design time and an improvement in early bug detection. The IPP process has been used by over 70 designers of the BrazilIP Network, a SystemC collaborative partnership, in the design of the Fenix system. An intermediate step in the Fenix design is a real-world multimedia platform called CINE-IP (demo available at http://www.brazilip.org.br/cine-ip), composed of MPEG4, MP3 decoders and an 8051 microcontroller. The application of the IPP methodology in the design of CINE-IP, and its impact in design productivity is thoroughly analyzed.

Sea-of-gates architecture

This paper deals with the development of sea-of-gates technology for the design of VLSI circuits. Sea-of-gates technology, also considered a second generation gate-array system, is discussed in detail. Its internal structure and the main physical aspects that differentiate sea-of-gates from conventional gate-arrays are presented. The advantages over the previous generation of gate-arrays, and for some circuits in comparison with full-custom technology, are discussed, together with its influence in the likely ASIC market.

FPGA-based architecture to speed-up scientific computation in seismic applications

Hardware accelerators like GPGPUs and FPGAs have been used as an alternative to conventional CPU architectures in scientific computing applications and have shown considerable speed-ups on them. In this context, this work presents an FPGA-based solution that explores efficiently the data reuse and spatial and time domain parallelism for the first computational stage of the reverse time migration (RTM) algorithm, the seismic modelling. We also implemented the same algorithm for some CPUs and GPGPU architectures and our results showed that an FPGA-based approach can be a feasible solution to improve performance. Experimental results showed similar performance when compared to the GPGPU and up to 28.91 times speed-up when compared to CPUs. In terms of energy efficiency, the FPGA is almost 23 times and 1.75 times more efficient than the CPU and GPGPU, respectively. We also discuss some other features and possible optimisations that can be included in the proposed architecture that can make this performance even better.

An environment for energy consumption analysis of cache memories in SoC platforms

The tuning of cache architectures in platforms for embedded systems applications can dramatically reduce energy consumption. The existing cache exploration environments constrain the designer to analyze cache energy consumption on single processor systems and worse, systems that are based on a single processor type. In this paper is presented the PCacheEnergyAnalyzer environment for energy consumption analysis of cache memory on SoC platforms. This is a powerful energy analysis environment that combines the use of efficient tools to provide static and dynamic energy consumption analysis, the flexibility to support the architecture exploration of cache memories on platforms that are not bound to a specific processor, and fast simulation techniques. The proposed environment has been integrated into the SoC modeling framework PDesigner, providing a user-friendly graphical interface allowing the integrated modeling and cache energy analysis of SoCs. The PCacheEnergyAnalyzer has been validated with four applications of the Mediabench suite benchmark.