Pavan Samudrala

Mix-and-match considerations for EUV insertion in N7 HVM

An optimal mix-match control strategy for EUV and 193i scanners is crucial for the insertion of EUV lithography at 7nm technology node. The systematic differences between these exposure systems introduce additional cross-platform mixmatch overlay errors. In this paper, we quantify the EUV specific contributions to mix-match overlay, and explore the effectiveness of higher-order interfield and intrafield corrections on minimizing the on-product mix-match overlay errors. We also analyze the impact of intra-field sampling plans in terms of model accuracy and adequacy in capturing EUV specific intra-field signatures. Our analysis suggests that more intra-field measurements and appropriate placement of the metrology targets within the field are required to achieve the on-product overlay control goals for N7 HVM.

Focus control enhancement and on-product focus response analysis methodology

With decreasing CDOF (Critical Depth Of Focus) for 20/14nm technology and beyond, focus errors are becoming increasingly critical for on-product performance. Current on product focus control techniques in high volume manufacturing are limited; It is difficult to define measurable focus error and optimize focus response on product with existing methods due to lack of credible focus measurement methodologies. Next to developments in imaging and focus control capability of scanners and general tool stability maintenance, on-product focus control improvements are also required to meet on-product imaging specifications. In this paper, we discuss focus monitoring, wafer (edge) fingerprint correction and on-product focus budget analysis through diffraction based focus (DBF) measurement methodology. Several examples will be presented showing better focus response and control on product wafers. Also, a method will be discussed for a focus interlock automation system on product for a high volume manufacturing (HVM) environment.

Overlay control for 7nm technology node and beyond

We demonstrate high volume manufacturing feasibility of 7 nm technology overlay correction requirement. This stateof- the-art overlay control is achieved by (i) overlay sampling optimization and advanced modeling, (ii) alignment and advanced process control optimization, (iii) multiple target overlay optimization, and (iv) heating control. We will also discuss further improvements in overlay control for 7 nm technology node and beyond including computational metrology, extreme ultraviolet and optic tools overlay matching control, high order alignment correction, tool stability improvement, and advanced heating control.

Novel methodology to optimize wafer alignment to enhance 14nm on product overlay

With continuous shrink in feature dimensions, overlay tolerance for fabrication of transistors is getting more stringent. Achieving good overlay is extremely critical in getting good yield in HVM environment. It is widely understood that good alignment during exposure is critical for better on product overlay [1]. Conventional methods to choose alignment marks on ASML scanners are based on comparing alignment key performance indicators (KPIs) including signal quality, grid repeatability, etc. It is possible that even with good alignment KPIs, OPO is still impacted. In this paper, we propose aspects that need to be monitored to choose proper alignment marks. LIS (Litho In-Sight) alignment, Ideal overlay/APC parameter signatures are used to determine and validate wafer alignment. LIS alignment ‘Target and Profile selection’ analysis enables us to determine best alignment strategy between multiple strategies/marks based on overlay measurements. Analysis includes examining wafer to wafer OPO variation which is key indicator for alignment robustness. Varying overlay parameters within lot would indicate either large process instability or alignment mark signal instability. It is possible that alignment marks depending on their segmentation can be very differently impacted with the process. Ideal overlay/APC signature stability indicates healthy process and wafer alignment. Having similar APC signatures at corresponding layers would mean that there is no major process or alignment issue.

Alignment solutions on FBEOL layers using ASML scanners

Wafers at FBEOL layers traditionally have higher stress and larger alignment signal variability. ASML’s ATHENA sensor based scanners, commonly used to expose FBEOL layers, have large spot size (~700um). Hence ATHENA captures the signal from larger area compared to the alignment marks which are typically ~40um wide. This results in higher noise in the alignment signal and if the surrounding areas contain periodic product structures, they interfere with the alignment signal causing either alignment rejects or in some cases- misalignment. SMASH alignment sensors with smaller spot size (~40um) and two additional probe lasers have been used to improve alignment quality and hence reduce mark/wafer rejects. However, due to the process variability, alignment issues still persist. For example, the aluminum grain size, alignment mark trench deposition uniformity, alignment mark asymmetry and variation in stack thicknesses all contribute to the alignment signal variability even within a single wafer. Here, a solution using SMASH sensor that involves designing new alignment marks to ensure conformal coating is proposed. Also new techniques and controls during coarse wafer alignment (COWA) and fine wafer alignment (FIWA) including extra controls over wafer shape parameters, longer scan lengths on alignment marks and weighted light source between Far Infra-Red laser (FIR) and Near Infra-Red (NIR) for alignment are presented. All the above mentioned techniques, when implemented, have reduced the wafer alignment reject rate from around 25% to less than 0.1%. Future work includes mark validation based on the signal response from the various laser colors. Finally, process monitoring using alignment parameters is explored.

Overlay optimization for 1x node technology and beyond via rule based sparse sampling

We demonstrate a cost-effective automated rule based sparse sampling method that can detect the spatial variation of overlay errors as well as the overlay signature of the fields. Our technique satisfies the following three rules: (i) homogeneous distribution of ~200 samples across the wafer, (ii) equal number of samples in scan up and scan down condition and (iii) equal number of sampling on each overlay marks per field. When rule based samplings are implemented on the two products, the differences between the full wafer map sampling and the rule based sampling are within 3.5 nm overlay spec with residuals M+3σ of 2.4 nm (x) and 2.43 nm (y) for Product A and 2.98 nm (x) and 3.32 nm (y) for Product B.

Scanner baseliner monitoring and control in high volume manufacturing

We analyze performance of different customized models on baseliner overlay data and demonstrate the reduction in overlay residuals by ~10%. Smart Sampling sets were assessed and compared with the full wafer measurements. We found that performance of the grid can still be maintained by going to one-third of total sampling points, while reducing metrology time by 60%. We also demonstrate the feasibility of achieving time to time matching using scanner fleet manager and thus identify the tool drifts even when the tool monitoring controls are within spec limits. We also explore the scanner feedback constant variation with illumination sources.

Analysis of wafer heating in 14nm DUV layers

To further shrink the contact and trench dimensions, Negative Tone Development (NTD) has become the de facto process at these layers. The NTD process uses a positive tone resist and an organic solvent-based negative tone developer which leads to improved image contrast, larger process window and smaller Mask Error Enhancement Factor (MEEF)[1]. The NTD masks have high transmission values leading to lens heating and as observed here wafer heating as well. Both lens and wafer heating will contribute to overlay error, however the effects of lens heating can be mitigated by applying lens heating corrections while no such corrections exist for wafer heating yet. Although the magnitude of overlay error due to wafer heating is low relative to lens heating; ever tightening overlay requirements imply that the distortions due to wafer heating will quickly become a significant part of the overlay budget. In this work the effects, analysis and observations of wafer heating on contact and metal layers of the 14nm node are presented. On product wafers it manifests as a difference in the scan up and scan down signatures between layers. An experiment to further understand wafer heating is performed with a test reticle that is used to monitor scanner performance.

Comparison study of diffraction based overlay and image based overlay measurements on programmed overlay errors

In this paper we will present the comparison study of these two methods on programmed errors of critical layers of 14nm technology node. Programmed OVL errors were made on certain fields during the exposure. Full coverage OVL measurements were performed using both IBO and DBO. Linear, HOPC and iHOPC modeling has been done from non-programmed fields. Then modeling has been subtracted from these certain programmed fields, and Reticle contribution was also calculated and subtracted. In this study, metrology measurement accuracy and stability can be feasible and more accurate OVL control is enabled by selecting better OVL measurement techniques.

Advanced overlay: sampling and modeling for optimized run-to-run control

In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the “sample plan” of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.