Pavan Shastry

A Surround View Camera Solution for Embedded Systems

Automotive surround view camera system is an emerging automotive ADAS (Advanced Driver Assistance System) technology that assists the driver in parking the vehicle safely by allowing him/her to see a top-down view of the 360 degree surroundings of the vehicle. Such a system normally consists of four to six wide-angle (fish-eye lens) cameras mounted around the vehicle, each facing a different direction. From these camera inputs, a composite bird-eye view of the vehicle is synthesized and shown to the driver in real-time during parking. In this paper, we present a surround view camera solution that consists of three key algorithm components: geometric alignment, photometric alignment, and composite view synthesis. Our solution produces a seamlessly stitched bird-eye view of the vehicle from four cameras. It runs real-time on DSP C66x producing an 880x1080 output video at 30 fps.

A 28nm programmable and low power ultra-HD video codec engine

Video codec standards like H.264 and HEVC are driving the need for high computation and high memory bandwidth in current SOCs. On the other hand, portable devices like smartphones and tablets are driving the need to reduce power consumption for enhanced battery life. In this paper, we present a scalable H.264 Ultra-HD video codec engine that dissipates 9 mW of decode and 18 mW of encode power (for a typical HP H.264 1080p30 bit-stream) in 28 nm low power process technology node using various low power optimization techniques across architecture, design, circuit, software and systems.

Ultra-low latency video codec for video conferencing

Video codec (e.g. HEVC, H.264, H.263, H.261) are used for real time video conferencing over internet. The amount of latency from end to end (or round trip) has significant impact on perceived quality of video call. This paper explains overall latency for entire signal chain with focus especially on video codec. The paper explains typical configuration to optimize overall latency of video processing down to range of 1 video frame processing time. The paper proposes new sub-frame based data flow to cut down overall latency to significantly to fraction of video frame. The paper proposes new design for video codec engine to enable sub-frame based data flow consisting of novel way of exchanging data between entropy engine and application, pre-fetching of video data without stalling video performance and sending of partial video output to network. The overall design enables reduction of processing latency of video engine from multiple frames to few lines of video. The overall solution on TIs Davinci series (DM816x) device achieves latency up-to 2 msec compared to prior art measurement of 33 msec resulting in better user experience due to large improvements in perceived visual quality.

A monolithic programmable Ultra-HD video codec engine

With advances in video coding standards like H.264 and HEVC coupled with those in the display technology, Ultra HD contents have started taking the mainstream. This is driving the need for high computation and memory bandwidth in current multi-media SOCs. In this paper, we present a monolithic multi-format video codec engine which achieves Ultra HD performance for H.264 High Profile, reduces the external memory bandwidth requirement by 2X as compared to its predecessor and takes only 5.9 mm2 of silicon area in a low power 28nm process.

Techniques to improve decoded video quality for erroneous H.264 bit streams in an asynchronous multiprocessor architecture

A conventional synchronous single processor decoder system can no longer cater to the demands of the market in terms of processing speed. A modern asynchronous multiprocessor architecture partitions the decoding functions into different processing cores so that real time decoding of high mega pixel streams is achieved by parallel execution. The number of processor cores is a balance between chip area, processing Mhz requirements and the latency incurred in the pipeline. Error handling on a modern asynchronous multiprocessor architecture is far more involved compared to its synchronous counterparts. This paper presents a software design and methodology in order to achieve better error resilience and concealment quality in a High Profile H.264 Universal Decoder on an asynchronous multiprocessor architecture. It involves robust error handling and error recovery, detection and handling of possible start code overrun, overcoming limitations due to the extremely efficient software design, improved error detection logic, and improvements in End of Picture Detection. Average PSNR improvement of 0.35 dB and maximum 4 dB has been obtained by these techniques, when tested on an error stream test suite of more than 100 randomly corrupted streams.