Subrangshu Das

A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC

In this paper, we present IVA-HD, a true multistandard, programmable, full HD video coding engine which adopts optimal hardware-software partitioning to achieve the low-power and area requirements of the OMAP 4 processor. Unlike the approach of using separate IPs for encoder and decoder, IVA-HD uses an integrated codec engine which is area efficient, as most of the decoder logic is reused for the encoder. IVA-HD is architected to perform stream-rate and pixel- rate processing in a single pipeline (that processes one 16x16 macroblock at a time), so as to support the latency requirements of video conferencing.

A 28nm programmable and low power ultra-HD video codec engine

Video codec standards like H.264 and HEVC are driving the need for high computation and high memory bandwidth in current SOCs. On the other hand, portable devices like smartphones and tablets are driving the need to reduce power consumption for enhanced battery life. In this paper, we present a scalable H.264 Ultra-HD video codec engine that dissipates 9 mW of decode and 18 mW of encode power (for a typical HP H.264 1080p30 bit-stream) in 28 nm low power process technology node using various low power optimization techniques across architecture, design, circuit, software and systems.

Reset careabouts in a SoC design

Advances in VLSI technology have enabled designers to integrate more functionality in one chip. One of the major design complexities arising from this is defining the reset architecture for a SoC, especially when there are multiple clock domains. Incorrect assumptions or overlooked issues might cause silicon bugs requiring costly re-spins or even worse to a missed opportunity. In this paper, various careabouts that help achieve first pass silicon success as well as reduced verification and manufacturing test generation effort with respect to the reset signal and the reset state are described.

A monolithic programmable Ultra-HD video codec engine

With advances in video coding standards like H.264 and HEVC coupled with those in the display technology, Ultra HD contents have started taking the mainstream. This is driving the need for high computation and memory bandwidth in current multi-media SOCs. In this paper, we present a monolithic multi-format video codec engine which achieves Ultra HD performance for H.264 High Profile, reduces the external memory bandwidth requirement by 2X as compared to its predecessor and takes only 5.9 mm2 of silicon area in a low power 28nm process.

Understanding System Level Caching Behavior in Multimedia SoC

A typical multimedia SoC consists of all or a subset of hardware components for image capture & processing, video compression and de-compression, computer vision, graphics and display processing. Each of these components access and compete for the limited bandwidth available in the shared external memory. Meeting latency (e.g., display) and throughput (e.g., video encode) is a critical problem to solve for such SoCs. In typical SoCs, this problem is solved using system level caches. However in this paper, we show results that indicate system level caches are not beneficial for multi-media traffic both in terms of DDR bandwidth savings as well as for latency reduction. We also show results of desirable features to improve multimedia performance in SoCs using a system cache.

Efficient system level cache architecture for multimedia SoC

A typical multimedia SoC consists of hardware components for image capture & processing, video compression and de-compression, computer vision, graphics and display processing. Each of these components access and compete for the limited bandwidth available in the shared external DDR memory. The traditional solution of using cache is not suitable for multimedia traffic. In this paper, we propose a novel cache architecture which is beneficial for multimedia traffic in terms of DDR bandwidth savings and latency reduction. The proposed cache architecture uses qualifier based splitter, multiple fully associative configurable features cache and an arbiter. The proposed cache architecture is evaluated using architectural model. The paper also proposes newer applications of this cache architecture as an infinite circular buffer for data buffer sharing across hardware components. The simulation results show 50% improvement in DDR bandwidth for video decoder traffic.

PowerAdviser: an RTL power platform for interactive sequential optimizations

Power has become the overriding concern for most modern electronic applications today. To reduce clock power, sequential clock gating is increasingly getting used over and above combinational clock gating. Given the complexity of manually identifying sequential clock gating changes, automatic tools are becoming popular. However, since these tools always work within the scope of the design and the constraints provided, they do not provide any insight into additional power savings that might still be possible. In this paper we present an interactive sequential analysis flow, PowerAdviser, which besides performing automatic sequential changes also provides information for additional power savings that the user can realize through manual changes. Using this new flow we have achieved dynamic power reduction upto 45% more than a purely automated flow.

DFT Challenges in Next Generation Multi-media IP

Multi-media based applications have increased immensely in the last few years. The need to have better video quality, higher recording and playback time, more video channels and faster time to market (TTM) requires DFT solutions that use core-based testing to allow concurrent IP and SOC development, scalable to support multiple technologies and eases the development of timing constraints. This paper describes the challenges and solutions used to address them.