Pavel Livshits

Toward fast malaria detection by secondary speckle sensing microscopy

Diagnosis of malaria must be rapid, accurate, simple to use, portable and low cost, as suggested by the World Health Organization (WHO). Despite recent efforts, the gold standard remains the light microscopy of a stained blood film. This method can detect low parasitemia and identify different species of Plasmodium. However, it is time consuming, it requires well trained microscopist and good instrumentation to minimize misinterpretation, thus the costs are considerable. Moreover, the equipment cannot be easily transported and installed. In this paper we propose a new technique named “secondary speckle sensing microscopy” (S3M) based upon extraction of correlation based statistics of speckle patterns generated while illuminating red blood cells with a laser and inspecting them under a microscope. Then, using fuzzy logic ruling and principle component analysis, good quality of separation between healthy and infected red blood cells was demonstrated in preliminary experiments. The proposed technique can be used for automated high rate detection of malaria infected red blood cells.

Local Oscillations of On-Die Supply Voltage—A Reliability Issue

On-die measurements of <i>V</i> _DD and <i>V</i> _SS voltages inside a 90-nm VLSI technology chip are presented. The results show local fluctuations in the <i>V</i> _DD and <i>V</i> _SS voltages with amplitudes that can reach, in severe cases, more than 10% of <i>V</i> _DD. These fluctuations can distort analog signals, cause immediate logic faults, and also aggravate other reliability wear-out mechanisms. Both measurements and simulations predict the aggravation of this phenomenon for future technologies.

Inter-symbol interference (ISI) in on-die transmission lines

The waveforms of a signal transmitted through single-ended on-die transmission lines, implemented by standard metal layers of a CMOS 45 nm technology node, have been experimentally studied. The influence of the active loss level of the lines, as well as of the impedance mismatch between the transmission line and its driver upon the signal distortion, and particularly upon the inter-symbol interference, is discussed.

Aggravated Electromigration of Copper Interconnection Lines in ULSI Devices Due to Crosstalk Noise

In this paper, the impact of crosstalk noise between two adjacent interconnection lines, namely, the aggressor and a victim line, upon electromigration (EM) and Joule-heating failure mechanisms in ULSI microchips has been studied. It was shown that the crosstalk noise leads to distortions of signal waveforms at the far end of the victim line, i.e., the signals supplied to the input of a far-end CMOS inverter. As a result, the shape of the inverters currents, flowing through the next-stage line (i.e., the line that loads this inverter), is modified in such a way that both EM and Joule heating of the next-stage line are aggravated. The studies reveal that the most deleterious scenario of the crosstalk noise is when the victim and aggressor are switching in opposite directions and the aggressor begins to switch around the trip point of the victims far-end CMOS inverter (i.e., when both nMOSFET and pMOSFET are open and in a triode mode). Thereby, the crosstalk noise is not only a signal integrity issue as it has been traditionally regarded but also a serious reliability concern that should be taken into account in corresponding reliability models.

Resonance properties of power supply and ground distribution networks in SoC

In this work, we propose a method for power grid modeling, where the grid consists of segments, which are regarded as transmission lines. The proposed approach allows the entire periodic power grid network to be represented for high-frequency AC simulations by only a small part of the power grid, terminated by impedance elements, equivalent to the impedance of the following power grid. The model performance has proved to be appropriate since the results correlate well with experimental results obtained from a 90 nm CMOS technology chip.

Supply signal fluctuations due to chip power grid resonance — a new reliability concern

On-die measurements of VDD and VSS signals inside a 90 nm technology chip are presented. The results show fluctuations in the VDD and VSS signals, which might constitute an important new reliability concern. These fluctuations also indirectly affect other reliability mechanisms, such as NBTI, HCI and TDDB. Simulations predict aggravation of this phenomenon for future technologies, which may prove to be a show stopper for further scaling.

New Super Resolving Techniques and Methods for Microelectronics

The third chapter deals with various approaches for superresolution that might be relevant for failure analysis of microelectronic chips and circuitry. In the first part of the chapter, we start by giving the basic theory on superresolution, describing the spatial degrees of freedom and the resolution limits of any imaging system. We discuss the Nyquist-Shannon sampling theorem and the image processing approaches capable of enhancing the geometric limitation of resolution. We provide useful processing and representation tools, such as the Wigner transform, which allows the representation of imaging systems with their existing resolution limits so that better understanding of how to overcome those limits can be achieved. Then, in the second part of the chapter, we present two novel image processing superresolution algorithms that are specifically applicable to failure analysis of microelectronic circuitry. The first image processing approach is based upon the iterative Papoulis–Gerchberg algorithm. The second image processing approach is based on the Radon transform. The applicability of both algorithms in enhancing the resolution of images of microelectronic chips during the failure analysis process is presented.

Improved Reliability and Functionality of Clock Networks in ULSI Devices Due to Lossy Transmission Line Modeling Method

In this paper, the ways to improve the functionality and reliability of Digital Signal Processors, used to support optical networks, have been studied. Specifically, supported on our finding from previous experimental studies that on-die global interconnects should be described by a distributed RLC model, we propose to model shielded lines, carrying the most critical signals, by a Lossy Transmission Line (LTRA) model. The proposed method obviates the need for tedious simulations, which also due to many inevitably required oversimplifications have a low correlation with a real circuit behavior. The SPICE simulated signal waveforms obtained at the far-end of shielded lines correlate well with experimentally measured waveforms within a typical 45 nm CMOS technology ULSI chip. Based on both, simulations and experimental measurements, we have construed criteria whereby we modified the CMOS driver strength selection guideline to conform to the distributed nature of on-die interconnection lines. The performed simulations on a multi-level clock H-tree structure from a high-performance core block indicate that the new approach considerably improves MOSFETs reliability and power dissipation.