Yefim Fefer

Inter-symbol interference (ISI) in on-die transmission lines

The waveforms of a signal transmitted through single-ended on-die transmission lines, implemented by standard metal layers of a CMOS 45 nm technology node, have been experimentally studied. The influence of the active loss level of the lines, as well as of the impedance mismatch between the transmission line and its driver upon the signal distortion, and particularly upon the inter-symbol interference, is discussed.

Resonance properties of power supply and ground distribution networks in SoC

In this work, we propose a method for power grid modeling, where the grid consists of segments, which are regarded as transmission lines. The proposed approach allows the entire periodic power grid network to be represented for high-frequency AC simulations by only a small part of the power grid, terminated by impedance elements, equivalent to the impedance of the following power grid. The model performance has proved to be appropriate since the results correlate well with experimental results obtained from a 90 nm CMOS technology chip.

Investigation of on-chip PLL irregularities under stress conditions - case study

In modern high performance VLSI design, on-chip phase locked loop (PLL) performance degradation due to intensive core switching activities is becoming an influential factor. Under certain borderline conditions, the PLL may become unstable. The analysis herein describes PLL irregularities under marginal mode, frequency and voltage conditions combined with intensive core operations. After lengthy analysis that included step-by-step elimination of all noise sources, the cause of instability was explained by coupling between a voltage spike on core power supply line and the internal control signal of the voltage controlled oscillator of the PLL through the chip substrate. The solution to the problem was suggested by changing the PLL dynamic characteristics. Through this investigation we studied the noise crosstalk issue in mixed mode (analog and digital) systems and also the PLL dynamics under stress conditions, which demonstrates the complexity of PLL analysis in a system-on-chip environment.

Automatic system for VLSI on-chip clock synthesizers characterization

Analyzing the ability of clock generation circuits to provide a high quality chip clock for synchronous systems is very critical. This is important in order to ensure stable functioning of such systems at the highest frequencies, in addition to ensuring reliable communications between core, on-chip peripherals, external peripherals and memory. We propose a clock synthesizer characterization system, which performs measurements automatically, according to the clock synthesizers mode, frequency, power supply voltage and ambient temperature. The system is intended to work in both quiet and noisy environments. The accuracy of the measurements, together with the systems high flexibility and speed, allows on-the-spot characterizations, which in turn results in a detailed, statistically reliable picture of the clock signals quality. Practical experience has shown that this system is effective, not only for clock synthesizer characterization, but for failure analysis as well.

A new approach for automated characterization of high speed serial interfaces of SoC

The testing approach described in the paper proposes to reduce the time required for HSSI characterization by testing the devices according to specially developed PHY specifications, instead of direct testing of all electrical parameters required by the supported standards, and introducing an automated testing setup, based on an automated active probing solution.

Inductance Considerations of on-Chip Interconnections for Best Electrostatic Discharge Protection Performance

The inductance of the on-die interconnection lines may cause voltage resonant effects under electrostatic discharge (ESD) stress. The phase difference of the resonating oscillations along different ESD current flow paths creates a significant local momentary voltage. Information on this inductance enables designers to take into consideration these voltage resonant effects in ESD protection design

Board design considerations for multilane SerDes bench testing

The considerations and challenges, involved in designing a board for SerDes characterization, are analyzed. Analysis of the sources for the distortion of the signal transmitted through the characterization board, as well as measures to mitigate these sources are proposed.

Novel method for debug of electrostatic discharge protection in VLSI circuits

A proposed method for failure analysis and debugging of electrostatic discharge protection in VLSI circuits is presented, based on low-energy non-destructive emulation of real ESD stress. It allows on-die current and voltage measurements during stress, providing a direct and clear conclusion about the proper functioning of the protection method, or a reason for failure