Pawel Sniatala

Low-voltage high-performance switched current memory cell

A new switched current (SI) memory cell is proposed in the paper. Analysis and simulations show very good properties of the cell. Layout of a sample and hold (SH) circuit composed of the memory cell is also presented. This SH circuit is a basic cell of bilinear integrators and delay lines, being components of one- and two-dimensional SI filters. The method and tools for automated design of such filters are briefly described.

SI-Studio, a layout generator of current mode circuits

The paper presents automatic layout generation of analog current mode circuits.Chip area, power consumption and speed operation is controlled.An experimental chip was fabricated in CMOS technology.The chip was tested in the environment based on FPGA.Measurement results of realized filter pairs and filter banks are presented. This work is the answer to the so far unsolved problem of generation of integrated circuits topography for current mode circuits. Synthesis methods corresponding to already existing digital methods are proposed. Among others - the following has been shown: a digital adaptation of the row strategy for analog cell design, as well as performance control of the circuits with respect to chip area, power consumption and speed operation. The proposed algorithms are integrated with the already-existing tools for automatic layout generation of analog circuits with behavioral description at the beginning. At each stage of the synthesis process - an architecture description in the VHDL-AMS language was used, which so far has been not useful to synthesize. On the basis of the elaborated expert system, layouts of a filter pair and a filter bank were generated. The circuits were fabricated in TSMC 0.18 µ m CMOS technology and results of measurements are presented. The elaborated approach makes a contribution to the realization of current mode circuits with complexity not achievable up to now.

Asphalt surfaced pavement cracks detection based on histograms of oriented gradients

Cracks are the most requiring type of pavement distresses to detect and classify automatically. Due to its nature are easily absorbed by other types of pavement surface damages. Moreover, the diversity of pavement surface makes the image detection system requiring efficient computer algorithms. The paper presents the solutions tested on surface distress data which were collected automatically using downward facing cameras placed orthogonally to road pavement axis. Presented results focus on the crack-type pavement distresses. The achieved accuracy of the transverse, longitudinal and meshing cracks recognition based on the initial dataset prepared especially for this system, show it has very good chances to work efficiently with large image datasets collected during the inspection car runs.

Hardware Realization Of The MPEG-7 Edge Histogram Descriptor

The paper presents hardware implementation of the MPEG-7 edge histogram descriptor. The testing circuit was described using VHDL language and synthesized into FPGA. The RC1000 board with a Xilinx Virtex V1000 FPGA was chosen as the target platform. Experimental results of the descriptor efficiency are presented too

Embedded platform for local image descriptor based object detection

The article presents novel idea of a hardware accelerated image processing algorithm for embedded systems. The system is based on the well known Fast Retina Keypoint (FREAK) local image description algorithm. The solution utilizes Field Programmable Gate Array (FPGA) as a flexible module that is used to implement hardware acceleration of a given part of the image processing algorithm. The approach presented in this paper is slightly different. Since we are using very fast FREAK descriptor it is not our purpose to implement full feature extraction algorithm in hardware but just its most time-consuming part which is brute force matcher based on the Hamming distance. Moreover our goal was to design very flexible system so that the feature detection and extraction algorithm can be replaced without any interruption in the hardware accelerated part.

Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits

This paper presents an improved clock-phase generator, able to provide two non-overlapping phases, with an accurate phase shift of 180 degrees. The circuit relies on a modified version of the classic NAND-based bi-phase clock generator but uses an equalizing transmission gate together with dedicated self-biased logic. Simulation results over PVT corners show that, when compared with the original bi-phase clock generator, the proposed circuit exhibits a reduction in the spread of the phase-skew error by a factor higher than 2.4 whilst dissipating similar power. Moreover, the proposed circuit does not require any kind of calibration.

CPLD Based Development Board for Mixed Signal Chip Testing

This paper presents an original testing board dedicated for SI ASIC chips. The board is based on a programmable logic device, which generates the required signals for the tested chip. The parameters of the signals are set with a simple interface. The project was written in a VHDL and implemented in Xilinx CPLD. The board was used to test a new structure of a SI integrator, and the results are also presented.

Automated design and layout generation for switched current circuits

Recent advances in VLSI technology in combinations with economical motivations results in drive to integrate the complete signal processing chain on a single ASIC or SOC. However, the luck of supporting CAD tools for the synthesis and layout generation of the analog blocks is the major bottleneck in the design of modern mixed signal VLSI circuits. The paper presents original methods and their implementation for automated design of the switched current (SI) blocks. The design flow includes programs for SI circuits synthesis and automated layout generation. As an example a design of current mirrors for SI filters is presented

Fully differential sigma-delta modulator structure for current-mode sensors

Many emerging systems, such as smart sensor interfaces for cyber-physical systems (CpS), require energy efficient analog-to-digital converters (ADCs). Low-order, continuous-time (CT), current-mode (CM) sigma-delta modulators (SDMs) can be an attractive solution due to their intrinsic ability to operate with ultra-low voltage signal swings, without requiring any voltage-mode amplifiers, whilst providing significant energy savings. A first-order, continuous-time, current-mode Sigma-Delta modulator (SDM) with high energy efficiency is proposed. The SDM, designed in a 65 nm CMOS technology.

Road structure analysis based on cross-section images processing

Road pavement structure analysis provides important information for road maintenance and renovation planning. Image processing methods applying to cross-section of the asphalt pavement can provide valuable information about the pavement structure and its quality. The paper presents a method to analyze a picture of a cross-section sample, taking into account aggregates size. The features that have been captured and quantified using 2-D images were limited to aggregates size. The elaborated algorithm and its implementation are presented. The tool is prepared as a part of a bigger system dedicated to road pavement analysis.