Andrzej Handkiewicz

Analog filter pair design on the basis of a gyrator–capacitor prototype circuit

The paper presents an algorithmic approach to a low-sensitivity design strategy for analog filter pairs based on a gyrator–capacitor prototype circuit. The general structure of the prototype circuit is proposed. It assumed that the generic structure of the prototype circuit can evolve, with the use of additional gyrators, into a circuit with increased redundancy. It is shown that symbolic analysis of the prototype circuit, used to formulate a set of nonlinear algebraic equations, is necessary to achieve a sufficiently high algorithm operation speed. To find a solution to this specific system of nonlinear algebraic equations, different numerical methods are compared. The modified Hooke and Jeeves algorithm is found to be the most effective. The elaborated algorithms and programs are illustrated with the seventh-order filter pair example. The obtained filter is better than the filter obtained using LC ladder structures with respect to chip area and power consumption, and these improvements are obtained without loss of sensitivity properties. Copyright

Switched-current technique for video compression and quantization

Portable consumer products need low-cost, low-power chips for realization of signal processing and image compression functions. In this paper a modification of such a chip for a digital video camera is presented. The chip contains an image sensing array composed of photodiodes, a two-dimensional DCT processor and an entropy coding section. The processor is designed in a switched-current (SI) technique and contains current mirrors and memory cells. In order to examine these elementary cells, an experimental chip in AMS 0.8 /spl mu/m technology was fabricated.

Low-voltage high-performance switched current memory cell

A new switched current (SI) memory cell is proposed in the paper. Analysis and simulations show very good properties of the cell. Layout of a sample and hold (SH) circuit composed of the memory cell is also presented. This SH circuit is a basic cell of bilinear integrators and delay lines, being components of one- and two-dimensional SI filters. The method and tools for automated design of such filters are briefly described.

SI-Studio, a layout generator of current mode circuits

The paper presents automatic layout generation of analog current mode circuits.Chip area, power consumption and speed operation is controlled.An experimental chip was fabricated in CMOS technology.The chip was tested in the environment based on FPGA.Measurement results of realized filter pairs and filter banks are presented. This work is the answer to the so far unsolved problem of generation of integrated circuits topography for current mode circuits. Synthesis methods corresponding to already existing digital methods are proposed. Among others - the following has been shown: a digital adaptation of the row strategy for analog cell design, as well as performance control of the circuits with respect to chip area, power consumption and speed operation. The proposed algorithms are integrated with the already-existing tools for automatic layout generation of analog circuits with behavioral description at the beginning. At each stage of the synthesis process - an architecture description in the VHDL-AMS language was used, which so far has been not useful to synthesize. On the basis of the elaborated expert system, layouts of a filter pair and a filter bank were generated. The circuits were fabricated in TSMC 0.18 µ m CMOS technology and results of measurements are presented. The elaborated approach makes a contribution to the realization of current mode circuits with complexity not achievable up to now.

Design automation of a lossless multiport network and its application to image filtering

The paper presents expert tools which are elaborated on the basis of synthesis method of lossless nonreciprocal multiport circuits, composed of gyrators and capacitors. The algorithms are written in C++ and the tools compose a user friendly environment for design automation of filters, filter pairs and filter banks. It is possible to design in this environment not only classical structures like Butterworth, Chebyshev, and Cauer (elliptic) filters. The lossless nonreciprocal prototype circuit allows to design more complex filters, including allpass sections necessary to improve filter phase characteristics. However, the most important possibility is to design multiport circuits, especially in the case of not fully determined filter specifications. On each stage of the design process VHDL-AMS is used to describe the circuits. The obtained prototype gyrator-capacitor circuit can be implemented in OTA-C, SC (switched-capacitor) or SI (switched-current) techniques to realize the filter in CMOS technology. In the paper SI technique is used for layout generation of an image filter in order to illustrate the elaborated synthesis algorithms and tools.

Switched-current implementation of two-dimensional DCT for image processing

Switched-current (SI) circuits are suitable to operate on the same chip with digital circuits in low-voltage supply. This property is very important for applications in portable devices like digital cameras. Switched-capacitor implementation of the two-dimensional (2D) discrete cosine transform (DCT) was reported in the literature. In this paper, the design method of a 2D DCT for SI implementation is presented. An experimental chip was fabricated in AMS CMOS 0.8 /spl mu/m technology. The results of testing are reported.

FPAA Accelerator for Machine Vision systems

This article presents a proposition of an FPAA-type programmable accelerator for image preprocessing. The structure of the accelerator is modelled basing on CPLD digital circuits. The innovation here – is using the current mode, which makes it possible to implement the accelerator in nanometre technologies. Another original solution proposed in the work is a reconfigurable multi-output current mirror. The article describes the hardware layer and a method for programming it. An implementation of an RGB-to-YCrCb colour space converter is presented. Moreover physical parameters obtained in post-layout simulations are presented as well. The solution can be used as a standalone programmable circuit or as an IPcore for a larger analogue-digital system. Streszczenie. W artykule przedstawiono propozycję programowalnego akceleratora typu FPAA do wstępnej obróbki obrazu. Struktura akceleratora wzorowana jest na cyfrowych układach CPLD. Innowacyjność polega na wykorzystaniu trybu prądowego, co umożliwia realizację akceleratora w technologiach nanometrowych. Kolejnym oryginalnym rozwiązaniem zaproponowanym w pracy jest rekonfigurowalne wielowyjściowe zwierciadło prądowe. W artykule omówiono warstwę sprzętową oraz metodę jej programowania. Zaprezentowano implementację konwertera przestrzeni barw RGB do YCrCb w akceleratorze i przedstawiono parametry fizyczne uzyskane w symulacjach post-layoutowych. Rozwiązanie może być wykorzystane jako samodzielny układ programowalny lub IP-core większego systemu analogowo-cyfrowego. (Akcelerator FPAA dla systemów wizyjnych).

CPLD Based Development Board for Mixed Signal Chip Testing

This paper presents an original testing board dedicated for SI ASIC chips. The board is based on a programmable logic device, which generates the required signals for the tested chip. The parameters of the signals are set with a simple interface. The project was written in a VHDL and implemented in Xilinx CPLD. The board was used to test a new structure of a SI integrator, and the results are also presented.

Switched-current filter design for image processing systems

The paper presents a design method of two-dimensional. (2-D) switched-current (SI) filters. Because of SI technique compatibility with the standard digital CMOS technology, it is very convenient to use such filters in image processing. Operation of a system containing 2-D filters in a pre-processing stage is described. Such a system can be implemented in portable one-chip devices like digital video cameras.

Automation of CMOS technology migration illustrated by RGB to YCrCb analogue converter

The paper illustrates a practical example of technology migration applied to the colour space converter realized in CMOS technology. The element has analogue excitation and response signals expressed in current mode. Such converter may be incorporated into an integrated vision sensor for preconditioning acquired image data. The idea of a computer software tool supporting the automated migration and design reuse is presented as the major contribution. The mentioned tools implement the Hooke-Jeeves direct search method for performing the multivariable optimization. Our purpose is to ensure transferring the circuit between usable fabrication technologies and preserving its functional properties. The colour space converter is treated as the case study for performance evaluation of the proposed tool in cooperation with HSPICE simulation software. The original CMOS technology files for Taiwan semiconductor (TSMC) plant were utilized for the research. The automated design migration from 180 nm into 90 nm resulted with obtaining compact IC layout characterized by a smaller area and lower power consumption. The paper is concluded with a brief summary that proves the usability of the proposed tool in designing CMOS cells dedicated for low power image processing.