Payman Behnam

Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs

By increasing the complexity of system on chip (SoC) designs formal equivalence verification and debugging have become more and more important. Lower level methods such as BDDs and SAT solvers suffer from space and time explosion problems to match sizes of industrial designs in formal equivalence verification and debugging. This paper proposes techniques to verify and debug datapath intensive designs based on a canonical decision diagram called Horner Expansion Diagram (HED). It allows us to check the equivalence between two models in different levels of abstraction, e.g., a Register Transfer Level (RTL) implementation and a non-cycle-accurate specification. In order to reduce the complexity of equivalence checking problem, we tackle the exponential path enumeration problem by automatically identifying internal equivalent conditional expressions as well as suitable merge points. Our debugging technique is based on introducing mutations into the buggy implementation and then observing if the specification is capable of detecting these changes. We make use of a simple heuristic to reduce the number of mutants when dealing with multiple errors. We report the results of deploying our equivalence verification technique on several industrial designs which show 16.8x average memory usage reduction and 8.0x speedup due to merge-point detection. Furthermore, our debugging technique shows 13.7x average memory usage reduction and 4.6x speedup due to using SMT solvers to find equivalent conditions. In addition, the proposed debugging technique can avoid the computation of unnecessary mutants so that the results show 2.9x average reduction of the number of mutants to be processed.

Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism

Arithmetic circuits require a verification process to prove that the gate level circuit is functionally equivalent to a high level specification or not. Furthermore, if two models are not equivalent, we need to automatically localize bugs and correct them with minimum user intervention. This paper presents a formal technique to verify and debug arithmetic systems including dividers. The proposed technique is based on a reverse-engineering mechanism of obtaining a high level model of the gate level implementation and also presenting the specification at a lower level of abstraction which makes the equivalence checking between two models possible. During this process, if two high level models are not equivalent, possible bugs can be localized and then corrected automatically if possible. We have applied our technique to a wide range of arithmetic circuits including dividers, multipliers and their combinations. Preliminary experimental results show robustness of the proposed technique in comparison with other contemporary methods in terms of the run time. In average, two orders of magnitude average speedup is obtained.

A probabilistic approach for counterexample generation to aid design debugging

In todays technology, verification and debugging have become important phases in the digital design process. In many of the prevailing debugging methods, counterexamples play an immense role. Hence generating fewer and more accurate counterexamples can aid in detecting additional bugs in a short run time. Today many approaches use Automatic Test Pattern Generation (ATPG) techniques to generate counterexamples for the purpose of debugging. This paper presents a highly accurate probabilistic method to generate fewer counterexamples at the gate level. The proposed method uses signal probability analysis to guide the counterexample generation process. Experimental results for ISCAS85 and ISCAS89 benchmarks show the effectiveness of our proposed method compared with the existing ATPG approaches.

Formally analyzing fault tolerance in datapath designs using equivalence checking

In this paper, we present an efficient formal approach to check the equivalence of synthesized Register Transfer Level (RTL) against the high level specification in the presence of pipelining transformations. With the proposed equivalence checking method, fault tolerance issues when some faults happen in the designs can be formally analyzed. Equivalence checking with the specification can reason about how quickly the design can come back to normal operations when some faults happen. To increase the scalability of our proposed method, we dynamically divide the designs into several smaller parts called segments by introducing dynamic cut-points. Then we employ Modular Horner Expansion Diagram (M-HED) to check whether the specification and the implementation are equivalent or not. Our proposed method enables us to deal with the equivalence checking problem for behaviorally synthesized designs even in the presence of pipelines for nested loops. The empirical results demonstrate the efficiency and scalability of our proposed method in terms of run-time and memory usage for several large designs synthesized by a commercial behavioral synthesis tool. Average improvements in terms of the memory usage and run time in comparison with SMT- and SAT-based equivalence checking are 16.7× and 111.9×, respectively.

In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms

A large amount of time and effort must be spent to ensure the correctness of a digital design. Although many Computer Aided Design (CAD) solutions have been provided to enhance efficiency of existing debugging approaches, they are suffering from shortage of efficient automatic correction mechanisms. In this paper, we introduce an in-circuit mutation technique for correcting design bugs in digital designs. The aim of this work is reducing correction time by connecting primitive gates into inputs of 6-to-1 multiplexers in the place of potential bugs and utilizing satisfiability (SAT) engine for choosing the correct gates. The empirical results demonstrate that our proposed method can correct multiple bugs in a design by targeting gate replacements and wires exchanges efficiently. Average improvements in terms of the runtime and success rate in correction for combinational circuits in comparison with the latest the existing method are 3.4× and 11.5%, respectively. These results for sequential circuits are 3.8× and 17% respectively.

Automatic Correction of Certain Design Errors Using Mutation Technique

In this paper, we introduce a new technique that makes use of satisfiability (SAT) based debugging techniques along with a mutation-based technique to correct certain design errors in digital designs automatically. The experimental results demonstrate that our proposed method enables us to locate and correct multiple bugs by targeting gate replacements and wire exchanging within reasonable run-time and memory usage for several designs.

Improving polynomial datapath debugging with HEDs

In this paper, we introduce a formal and scalable debugging approach to derive a reduced ordered set of design error candidates in polynomial datapath designs. To make our debugging method scalable for large designs, we utilize a Modular Horner Expansion Diagram (M-HED), which has been shown to be a scalable high level decision model. In our method, we extract data dependency graphs from the polynomial datapath designs using static slicing. Then we combine backward and forward path tracing to extract a reduced set of error candidates. In order to increase the accuracy of the method in the presence of multiple design errors, we rank the error candidates in decreasing order of their probability of being an error using a proposed priority criterion. In order to evaluate the effectiveness of our method, we have applied it to several large designs. The experimental results show that the proposed method enables us to locate even multiple errors with high accuracy in a short run time.

A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs

By increasing the complexity of digital systems, verification and debugging of such systems have become a major problem and economic issue. Although many computer aided design (CAD) solutions have been suggested to enhance efficiency of existing debugging approaches, they are still suffering from lack of providing a small set of potential error locations and also automatic correction mechanisms. On the other hand, the ever-growing usage of digital signal processing (DSP), computer graphics and embedded systems applications that can be modeled as polynomial computations in their datapath designs, necessitate an effective method to deal with their verification, debugging and correction. In this paper, we introduce a formal debugging approach based on static slicing and dynamic ranking methods to derive a reduced ordered set of potential error locations. In addition, to speed up finding true errors in the presence of multiple design errors, error candidates are sorted in decreasing order of their probability of being an error. After that, a mutation-based technique is employed to automatically correct bugs even in the case of multiple bugs. In order to evaluate the effectiveness of our approach, we have applied it to several industrial designs. The experimental results show that the proposed technique enables us to locate and correct even multiple bugs with high confidence in a short run time even for complex designs of up to several thousand lines of RTL code.

Hybrid history-based test overlapping to reduce test application time

In spite of significant efforts in circuit testing, sequential circuit testing has remained a challenging problem. Existing test solutions like scan methods are proposed to facilitate Automatic Test Pattern Generation (ATPG), however, these methods suffer from large area and delay overhead. In this paper, a new hybrid history-based test overlapping method is presented to reduce test time in scan-based sequential circuits while almost no extra hardware overhead is imposed to the circuit. Experimental results show 30% reduction on average test time in comparison with existing works.

Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach

Fault diagnosis is one of the most important phases in the VLSI design cycle. This paper proposes a probabilistic solution for the fault diagnosis in the sequential scan-based circuits. Our approach uses a signal probability analysis to score and rank potential fault locations. The ranking results are exploited to reduce the search space for exact diagnosis approaches. The experimental results show how this technique can increase the scalability and speed of satisfiability (SAT)-based diagnosis approach.