Pei-I Wang

Real time resistivity measurements during sputter deposition of ultrathin copper films

Measurements of the electrical resistivity of thin copper films sputtered onto silicon dioxide, in real time, are reported. The electrical resistivity is shown to strongly depend on the film’s thickness for thicknesses below the bulk mean free path of copper (39 nm). Model fits to the electrical resistivity combined with ex situ atomic force microscopy and transmission electron microscopy suggest that the average grain size plays a dominant role in the resistivity during growth. Furthermore, observations are made on the relaxation of the electrical resistivity after the growth (by sputtering) is terminated, at room temperature. Both the magnitude and the time scale of change in the electrical resistivity are observed to be a function of the film’s thickness.

Low temperature melting of copper nanorod arrays

We report the melting of nanorod arrays of copper at temperatures much lower than its bulk melting point (1083°C). The Cu nanorods were produced by an oblique angle sputter deposition technique through a physical self-assembly mechanism due to the shadowing effect. The as-deposited nanorods were ∼2300nm in length, ∼100nm in diameter, and separated from each other with gaps varying between ∼10 and ∼30nm. The melting process was investigated through the analysis of scanning electron microscopy, transmission electron microscopy, and x-ray diffraction measurements. Start of premelting (or surface melting) has been observed to occur at annealing temperature ∼400°C under vacuum (10−6Torr). As the temperature was raised the arrays of Cu nanorods started to coalesce and formed a dense continuous film with a (111) texture at ∼550°C. The results of this work may be useful for low temperature soldering applications.

Low Temperature Wafer Bonding by Copper Nanorod Array

A vast array of Cu nanorods with a diameter of 10-20 nm grown by an oblique angle deposition technique was utilized as an adhesive layer for bonding 200 mm Si wafers at low temperatures. The focus ion beam/scanning electron microscope images illustrate that the Cu nanorod array underwent coalescence readily upon a bonding temperature at 200°C. Upon 400°C, a dense Cu bonding layer with homogeneous structure was achieved. A fully dense bonding structure was also obtained upon a lower bonding temperature at 300°C followed by a postannealing at 400°C in a reducing ambient.

Inductively Coupled Hydrogen Plasma-Assisted Cu ALD on Metallic and Dielectric Surfaces

Plasma-assisted atomic layer deposition (ALD) of Cu, via Cu I I (tmhd) 2 (tmhd = tetramethyl-3,5-heptanedionate) and an inductively coupled hydrogen plasma, is shown on metallic and dielectric surfaces. Nonselective deposition was achieved on SiO 2 , Au, and TaN x in a temperature range between 60 and 400°C. Deposition was self-limiting from ∼90 to 250°C. A novel method to determine self-limiting behavior of the first half-reaction is presented; it is determined by pulsing the precursor once, for a long time, and the resulting growth is measured by Rutherford backscattering spectrometry. Further, saturation curves for plasma-assisted ALD of each half-reaction and as a function of purging time were also determined. In contrast, thermal ALD via Cu I I (tmhd) 2 and H 2 was attempted and was very slow within the self-limiting temperature range. These experiments were undertaken on all the metallic and dielectric surfaces studied here including a plasma-assisted atomic layer deposited Cu seed.

Texture of Ru columns grown by oblique angle sputter deposition

Ru films were sputter deposited on native oxide p-Si(100) substrates under normal incidence and oblique angle incidence with and without substrate rotation. We characterized the crystalline texture and morphology of the Ru films by x-ray diffraction, transmission electron microscopy, and scanning electron microscopy. For the case of normal incidence, a smooth, uniform surface layer was observed, and pole figure analysis showed coexisting {101¯0}, {0002}, and {101¯1} normally oriented textures. For oblique angle incidence, we found that the films grown by uniform substrate rotation consist of isolated, vertical columnar structures with a clear pyramidal-shaped apex and display a normal {101¯0} fiber texture. Individual vertical columns were found to possess a single-crystal structure. In comparison, Ru films grown without substrate rotation possess a slanted columnar structure. They mainly show a tilted {101¯1}{101¯0} two-orientation (II-O) texture, with non-negligible {101¯0}{112¯0} and {0002} {112¯0} II-...

Novel growth mechanism of single crystalline Cu nanorods by electron beam irradiation

Single-crystal Cu nanorods have been fabricated on carbon films by manipulating electron beam irradiation on a Cu powder charge in a transmission electron microscope (TEM). By adjusting the intensity of the electron beam, we observed lively nucleation and growth of the Cu nanorods with the TEM. Individual Cu nanorods are straight with diameters ranging from 40 to 50 nm. The length of the rods is controlled by e-beam irradiation duration, and can be extended to . Selective area electron diffraction showed that the sidewalls of the Cu nanorods were associated with the (110) planes, while facets on the tips were associated with the (111) planes. We believe that the growth process is mainly controlled by high surface mobility of Cu atoms on the C surface, and surface diffusion of the Cu atoms from high surface energy planes to low surface energy planes of the Cu nanorods.

Conduction Mechanisms of Ta/Porous SiCOH Films under Electrical Bias

In the present study, the electrical characteristics of metal-insulator-semiconductor capacitors with Cu and Ta electrodes on porous SiCOH dielectric subjected to bias-temperature stress (BTS) are investigated. The capacitor with Cu electrode exhibits stable capacitance-voltage (C-V) characteristics after being subjected to BTS of 0.5 MV/cm at 200°C, while Ta ions readily drift into porous SiCOH under the BTS of 0.5 MV/cm and a lower temperature at 150°C, as indicated by the observation of a larger flatband voltage shift during C-V sweep afterward. The leakage behavior of porous SiCOH is investigated using a voltage ramp method after the capacitors are subjected to BTS to study the conduction mechanism associated with the metal-ion drift into the dielectric. It appears that the leakage of capacitors with Ta electrodes starts to increase after BTS and falls into the Poole-Frenkel conduction regime, indicating that Ta ions drift into porous low-k under BTS and subsequently act as electron traps. The leakage of capacitors with Cu electrodes, however, retains almost the same characteristics as those before BTS, suggesting that the increase of leakage for capacitors with Ta electrodes is induced by the drifted Ta ions instead of the degradation of dielectric material.

Kinetics of Ta ions penetration into porous low-k dielectrics under bias-temperature stress

It is known that Ta, a popular diffusion barrier material, can itself penetrate into low-k dielectrics under bias-temperature stress. In this work, we derived a model which directly correlates the diffusivity of Ta ions to the rate of flatband voltage shift (FBS) of the Ta/methyl silsesquixane (MSQ)/Si capacitors. From our experimentally measured constant FBS rate, the Ta diffusivity and activation energy were determined. It appears that an increase in the porosity of MSQ film enhances the Ta diffusivity but does not affect the associated activation energy. This suggests the Ta ion diffusion is mainly through interconnected pore surfaces.

Low Temperature Copper-Nanorod Bonding for 3D Integration

Wafer bonding is an emerging technology for fabrication of complex three-dimensional (3D) structures; particularly it enables monolithic wafer-level 3D integration of high performance, multi-function microelectronic systems. For such a 3D integrated circuits, lowtemperature wafer bonding is required to be compatible with the back-end-of-the-line processing conditions. Recently our investigation on surface melting characteristics of copper nanorod arrays showed that the threshold of the morphological changes of the nano-rod arrays occurs at a temperature significantly below the copper bulk melting point. With this unique property of the copper nanorod arrays, wafer bonding using copper nanorod arrays as a bonding intermediate layer was investigated at low temperatures (400 °C and lower). 200 mm Wafers, each with a copper nanorod array layer, were bonded at 200 – 400 °C and with a bonding down-force of 10 kN in a vacuum chamber. Bonding results were evaluated by razor blade test, mechanical grinding and polishing, and cross-section imaging using a focus ion beam/scanning electron microscope (FIB/SEM). The FIB/SEM images show that the copper nanorod arrays fused together accompanying by a grain growth at a bonding temperature of as low as 200 °C. A dense copper bonding layer was achieved at 400 °C where copper grains grew throughout the copper structure and the original bonding interface was eliminated. The sintering of such nanostructures depends not only on their feature size, but also significantly influenced by the bonding pressure. These two factors both contribute to the mass transport in the nanostructure, leading to the formation of a dense bonding layer.

Novel photocurable epoxy siloxane polymers for photolithography and imprint lithography applications

Polyset epoxy siloxane (PES) polymer is ultraviolet (UV) curable with photoinitiator chemistry based on cationic polymerization. In the present work the authors have investigated the photodefinition characteristics of the epoxy siloxane polymers using photolithography and imprint lithography. The scanning electron microscopic images of the UV-cured patterns exhibit appealing resolution of micrometer scale features for photolithography processes. The imprint lithography has been examined with features smaller than 200 nm. In conjunction with the promising dielectric properties, epoxy siloxane polymers are particularly useful for applications such as the redistribution layer in packaging of integrated circuits.