Pei Weihua

A flexible capacitive tactile sensor array with micro structure for robotic application

A flexible capacitive tactile sensor array with micro needle structure is proposed in this paper for robotic application. Micro needle layer made of polydimethylsiloxane (PDMS) is sandwiched between the upper electrode layer made of PDMS and the bottom electrode layer fabricated on polyester (PET) film. The PDMS material renders the device adequate flexibility as it can be rolled into a cylinder. The single cell size in the fabricated 4 × 4 sensors array is 0.7 × 0.5 cm2 and the initial capacitance of each cell is 0.86 pF. The fabricated cell shows a sensitivity of 3.26%/mN within the full scale range of 1 kPa. The micro needle structure gives better repeatability and stability. The maximum error during each measurement is about 3.2%, while the minimum error is about 1.2%.概要创新点面向机器人触觉恢复的广大市场需求, 本文提出了一种具有微针结构的柔性触觉传感器. 微针结构作为电介质层, 被夹在上下电极层之间, 形成平行板电容. 微针采用PDMS(聚二甲基硅氧烷)材料, 以保障器件的柔软性和可伸缩性. 微针结构的使用增加了器件的稳定性, 延长了器件的使用寿命. 在制成的4 × 4 检测阵列中, 单个检测单元大小为0.7 cm × 0.5 cm, 电容初值为0.86 pF. 经多次压按测试, 结果显示该阵列的测量范围为1 kPa, 检测精度为3.26 %/mN. 相同压力在多次检测中, 最大输出偏移为3.2%, 最小为1.2%.

Low power CMOS preamplifier for neural recording applications

A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extracellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The −3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1 μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.

A multi-channel fully differential programmable integrated circuit for neural recording application

A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4th-order Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter (SAR ADC), and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77 μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.

A novel linear microprobe array for the fabrication of neural microelectrodes

A novel linear microprobe array (LMPA) has been developed by a conventional microfabrication method from silicon. The LMPA leverages the properties of conventional microwire with additional features of naturally formed regular spacing. With the help of periodic microprobe arrays and double-side V-grooves fabricated in advance between each pair of the two microprobes’ rear ends, the number of microprobe units for assembly in one array can be flexibly chosen by cleavage fracture from the LMPA. The fabrication method was demonstrated and the prototype device was assessed by electrochemical impedance spectroscopy (EIS) and in vivo test. The SNR of the spikes recorded was 6.

Subretinal Implantable Micro Photodetector Array

A subretinal implant device, microphotodiode array, which can partly imitate the function of photoreceptor cells, was presented. Process to fabricate the MPDA and characteristics of the MPDA in vivo were described.

Dry Electrode Based Wearable Wireless Brain–Computer Interface System

Brain–computer interface (BCI) technology is a key issue in neural engineering, which can manipulate machine by electroencephalography (EEG). An important question surrounding the use of the BCI is the design of a wearable electroencephalography recording and processing equipment. We report the design and fabrication of a novel system based on dry electrodes, in which skin preparation and application of electrolytic gel are not required. In this study, an EEG-based BCI system, which includes a wireless transmitter module and an receiver module was designed, EEG is acquired using dry electrodes, amplified and processed by an application-specific integrated circuit (ASIC), and transmitted to the receiver by RF chip. The BCI system can obtain the subject’s degree of concentration, and those trained subjects have the ability of controlling the machine by changing their EEG signals. A experiment that controlling a toy car using the BCI system is successfully performed. The wearable transmitter module weighs 39 g only and easy to wear. The transmitter consumes 60 mW of dc power and generates an output power of 0 dBm. The BCI system is suitable for long-term EEG monitoring in users’ daily life. This system is feasible for further extension.

The Application of Parallel Optical Transmitter and Receiver Modules in Communication Subsystems

A new 12 channels parallel optical transmitter module in which a vertical cavity surface emitting laser (VCSEL) has been selected as the optical source is capable of transmitting 37.5 Gbps date over hundreds meters. A new 12 channels parallel optical receiver module in which a GaAs PIN (p-intrinsic-n-type) array has been selected as the optical receiver unit is capable of responding to 30 Gbps date. A transmission system based on a 12 channels parallel optical transmitter module and a 12 channels parallel optical receiver module can be used as a 10 Gbps STM-64 or an OC-192 optical transponder. The parallel optical modules and the parallel optical transmission system have passed the test in laboratory

Simulation of A Monolithically Integrated CMOS Bioamplifier for EEG Recordings

A monolithically integrated CMOS bioamplifier is presented in this paper for EEG recording applications. The capacitive-coupled circuit input structure is utilized to eliminate the large and random DC offsets existing in the electrode-tissue interface. Diode-connected NMOS transistors with negative voltage between gate and source are candidates for large resistors necessary to the bioamplifier. A passive BEF (Band Eliminator Filter) can reduce 50 Hz noise disturbance strength by more than 60 dB. A novel analysis approach is given to help determine the noise power spectral density. Simulation results show that the two-stage CMOS bioamplifier in a closed-loop capacitive feedback configuration provides an AC in-band gain of 39.6 dB, a DC gain of zero, and an input-referred noise of 87 nVrms integrated from 0.01 Hz to 100 Hz.

Subretinal implantable artificial photoreceptor

The present study reports a subretinal implant device which can imitate the function of photoreceptor cells. Photodiode (PD) arrays on the chip translate the incident light into current according to the intensity of light. With an electrode at the end of every photodiode, the PDs transfer the current to the remnant healthy visual cells such as bipolar cells and horizontal cells and then activate these cells. Biocompatible character of the materials and artificial photoreceptor itself were tested and the photoelectric characteristics of the chips in simulative condition were described and discussed.

Circuit design and simulation of a CMOS-based preamplifier for brain neural signals

A novel CMOS-based preamplifier for amplifying brain neural signal obtained by scalp electrodes in brain-computer interface (BCI) is presented in this paper. By means of constructing effective equivalent input circuit structure of the preamplifier, two capacitors of 5 pF are included to realize the DC suppression compared to conventional preamplifiers. Then this preamplifier is designed and simulated using the standard 0.6 /spl mu/m CMOS process technology model parameters with a supply voltage of 5 volts. With differential input structures adopted, simulation results of the preamplifier show that the input impedance amounts to more than 2 Gohm with brain neural signal frequency of 0.5 Hz-100 Hz. The equivalent input noise voltage is 18 nV/Hz/sup 1/2 /. The common mode rejection ratio (CMRR) of 112 dB and the open-loop differential gain of 90 dB are achieved.