Pei-Yu Huang

Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms

The capability of predicting the temperature profile is critically important for timing estimation, leakage reduction, power estimation, hotspot avoidance and reliability concerns during modern IC design. This paper presents an accurate and fast analytical full-chip thermal simulator for early-stage temperature-aware chip design. By using the generalized integral transforms (GIT), an accurate formulation is derived to estimate the temperature distribution of full-chip with a truncated set of spatial bases which only needs very small truncation points. Then, we develop a fast Fourier transform like evaluating algorithm to efficiently evaluate the derived formulation. Experimental results confirm that the proposed GIT-based analyzer can achieve an order of magnitude speedup compared with a highly efficient Greens function-based thermal simulator. Finally, we propose a 3-D IC thermal simulator and demonstrate its efficiency and accuracy.

A multiple supply voltage based power reduction method in 3-D ICs considering process variations and thermal effects

In this paper, a grid-based multiple supply voltage (MSV) assignment method is presented to statistically minimize the total power consumption of 3-D IC. This method consists of a statistical electro-thermal simulator to get the mean and variance of on-chip, a thermal-aware statistical static timing analysis (SSTA) to take into account the thermal effect on circuit timing, the statistical power delay sensitivity-slack product to be the optimization criterion, and an incremental update of statistical timing to save the runtime. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of the thermal effect in the circuit simulation is imperative.

An Aggregation-Based Algebraic Multigrid Method for Power Grid Analysis

This paper develops an aggregation-based algebraic multigrid (AbAMG) method to efficiently analyze the power grids. Different from the conventional algebraic multigrid (AMG) scheme, an innovative constructing method of global inter-grid mapping operator is employed to not only enhance the sparsity of coarse grid operator for reducing the computational complexity but also solve the problem with better convergent rate. The proposed method can solve the circuit with size over two millions in 167.6 CPU seconds (including DC analysis, and transient analysis with 50 time steps), and the maximum error is less than 1%. The significant runtime improvement, over 26times faster than the InductWise (Chen et al., 2003) and over 1.25times faster than the conventional AMG method, and less memory usage, 40% of the memory usage in (Chen et al., 2003) are demonstrated

Stochastic thermal simulation considering spatial correlated within-die process variations

In this work, we develop a statistical thermal simulator including the effect of spatial correlation under within-die process variations. This method utilizes the Karhunen-Loève (KL) expansion to model the physical parameters, and apply the Polynomial Chaoses (PCs) and the stochastic Galerkin method to tackle stochastic heat transfer equations. We demonstrate the accuracy and efficiency of our simulator by comparing with the Monte Carlo simulation, and point out that the stochastic thermal analysis is essential to provide a robust estimation of temperature distribution for the thermal-aware design flow.

LUTSim: A Look-Up Table-Based Thermal Simulator for 3-D ICs

To sustain Moores law, three-dimensional integrated circuit (3-D IC) is a promising solution to achieve high performance and low cost targets. However, its operating temperature is higher than that of a 2-D IC because of its high power density of stacked dies and ill of heat dissipation capability. Therefore, on-chip thermal effects have become major concerns of 3-D ICs. Utilizing look-up table approach, this paper, LUTSim, provides two thermal simulation engines, I-LUTSim and S-LUTSim, to efficiently calculate the thermal profile of a 3-D IC. I-LUTSim is suitable for full-chip thermal analysis, and S-LUTSim is suited for incremental-thermal updating. With utilizing the prebuilt tables, compared with a commercial tool ANSYS, the absolute error of I-LUTSim is less than 0.29%. Moreover, with negligible loss of accuracy, I-LUTSim can be 38.8 times faster than a well-known matrix solver SuperLU for performing full-chip thermal simulation. Besides, S-LUTSim can be over 1.05 million times faster than SuperLU for adjusting the thermal profile after inserting/removing a through silicon via.

I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs

This work presents an iterative look-up table based thermal simulator, I-LUTSim, to efficiently estimate the temperature profile of three-dimensional integrated circuits. I-LUTSim includes two stages. First, the pre-process stage constructs thermal impulse response tables. Then, the simulation stage iteratively calculates the temperature profile via the table lookup. With this two-stage scheme, the maximum absolute error of I-LUTSim is less than 0.41% compared with that of a commercial tool ANSYS. Moreover, I-LUTSim is at least an order of magnitude faster than a fast matrix solver SuperLU [1] for the full-chip temperature simulation.

Statistical electro-thermal analysis with high compatibility of leakage power models

In this work, a statistical electro-thermal analyzer with high compatibility of power model is developed. The developed analyzer takes both the easily implementing advantage of Monte Carlo method and the fast convergent advantage of stochastic analysis method to effectively solve the statistical electro-thermal problem. Experimental results indicate that the developed electro-thermal analyzer can be orders of magnitude faster than the Monte Carlo method under the same accuracy level. The computational time is only 1.16 seconds for a design with over one million gates, and the maximum errors are only 0.34% and 1.84%, compared with the Monte Carlo method, for estimating the mean and the standard deviation profiles of full-chip temperature distribution, respectively.

Full-chip thermal analysis for the early design stage via generalized integral transforms

The capability of predicting the temperature profile is critically important for circuit timing estimation, leakage reduction, power estimation, hotspot avoidance, and reliability concerns during modern IC designs. This paper presents an accurate and fast analytical full-chip thermal simulator for the early-stage temperature-aware chip design. By using the technique of generalized integral transforms (GIT), our proposed method can accurately estimate the temperature distribution of full-chip with very small truncation points of bases in the spatial domain. We also develop a fast Fourier transform (FFT) like evaluating algorithm to efficiently evaluate the temperature distribution. Experimental results confirm that our GIT based analyzer can achieve an order of magnitude speedup compared with a highly efficient Greens function based method.

On-chip statistical hot-spot estimation using mixed-mesh statistical polynomial expression generating and skew-normal based moment matching techniques

This work introduces the concept of thermal yield profile for the hot-spot identification with considering process variations and provides an efficient estimating technique for the thermal yield profile. After executing a mixed-mesh strategy for generating statistical polynomial expression of the on-chip temperature distribution, the thermal yield profile is obtained by a skew-normal based moment matching technique. Comparing with the Monte Carlo method, experimental results demonstrate that our method can efficiently and accurately estimate the thermal yield profile. With the same level of accuracy, our skew-normal based method achieves 215x speedup over the state of the art, APEX [1], for estimating the thermal yield profile. Moreover, results show that our mixed-mesh statistical polynomial expression generator achieves 130x speedup over the statistical collocation based method [2] and still accurately estimates the thermal yield profile.

Hierarchical power delivery network analysis using Markov chains

This paper proposes a Markov chain based hierarchical method to efficiently analyze the power delivery network. After the network being partitioned into several subnetworks, each subnetwork is transformed into a local Markov chain. Then, the connective relations between all subnetworks are modeled as a global Markov chain. Finally, those local and the global Markov chains are incorporated to build a hierarchical bipartite Markov chain engine to analyze the power delivery network. The experimental results not only demonstrate the accuracy of proposed method compared with a very accurate time domain solver [1], but also show its significant runtime improvement, over 200 times faster than the InductWise [1] and over 10 times faster than the IEKS method [2], and less memory usage.