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Dive into the research topics where Shih-An Yu is active.

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Featured researches published by Shih-An Yu.


IEEE Journal of Solid-state Circuits | 2010

A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications

Ajay Balankutty; Shih-An Yu; Yiping Feng; Peter R. Kinget

Supply voltage reduction with process scaling has made the design of analog, RF and mixed mode circuits increasingly difficult. In this paper, we present the design of an ultra-low voltage, low power and highly integrated dual-mode receiver for 2.4-GHz ISM-band applications. The receiver operates reliably from 0.55-0.65 V and is compatible with commercial standards such as Bluetooth and ZigBee. We discuss the design challenges at low voltage supplies such as limited fT for transistors and higher nonlinearities due to limited available signal swing, and present the architectural and circuit level design techniques used to overcome these challenges. The highly integrated receiver prototype chip contains RF front-end circuits, analog baseband circuits and the RF frequency synthesizer and was fabricated in a standard digital 90-nm CMOS process; it achieves a gain of 67 dB, noise figure of 16 dB, IIP3 of -10.5 dBm, synthesizer phase noise of - 127 dBc/Hz at 3-MHz offset, consumes 32.5 mW from 0.6 V and occupies an active area of 1.7 mm2.


IEEE Journal of Solid-state Circuits | 2006

A Quantization Noise Suppression Technique for

Yu-Che Yang; Shih-An Yu; Yu-Hsuan Liu; Tao Wang; Shey-Shi Lu

The first circuit implementation of quantization noise suppression technique for DeltaSigma fractional- N frequency synthesizers using reduced step size of frequency dividers is presented in this paper. This technique is based on a 1/1.5 divider cell which can reduce the step size of the frequency divider to 0.5 and thus the reduced step size suppresses the quantization noise by 6 dB. This frequency synthesizer is intended for a WLAN 802.11a/WiMAX 802.16e transceiver. This chip is implemented in a 0.18-mum CMOS process and the die size is 1.23 mm times 0.83 mm. The power consumption is 47.8 mW. The in-band phase noise of -100 dBc/Hz at 10 kHz offset and out-of-band phase noise of -124 dBc/Hz at 1MHz offset are measured with a loop bandwidth of 200 kHz. The frequency resolution is less than 1 Hz and the lock time is smaller than 10 mus


IEEE Journal of Solid-state Circuits | 2009

DeltaSigma

Shih-An Yu; Peter R. Kinget

We present ultra-low-voltage circuit design techniques for a fractional-N RF synthesizer with two-point modulation which was realized in 90-nm CMOS using only regular VT devices.; the voltage controlled oscillator, phase-frequency detector and charge pump operate from a 0.5 V supply while the divider uses a 0.65 V supply. The frequency synthesizer achieves a phase noise better than -120 dBc/Hz at 3 MHz, while consuming 6 mW. A calibration technique to equalize the gain between the two modulation ports is introduced and enables phase/frequency modulation beyond the loop bandwidth of the phase-locked loop. Measurement results for 2-Mb/s GFSK modulation are presented.


IEEE Journal of Solid-state Circuits | 2002

Fractional-

Ming-Chou Chiang; Shey-Shi Lu; Chinchun Meng; Shih-An Yu; Shih-Cheng Yang; Yi-Jen Chan

The realization of matched impedance wide-band amplifiers fabricated by InGaP-GaAs heterojunction bipolar transistor (HBT) process is reported. The technique of multiple feedback loops was used to achieve terminal impedance matching and wide bandwidth simultaneously. The experimental results showed that a small signal gain of 16 dB and a 3-dB bandwidth of 11.6 GHz with in-band input/output return loss less than -10 dB were obtained. These values agreed well with those predicted from the analytic expressions that we derived for voltage gain, transimpedance gain, bandwidth, and input and output impedances. A general method for the determination of frequency responses of input/output return losses (or S/sub 11/, S/sub 22/) from the poles of voltage gain was proposed. The intrinsic overdamped characteristic of this amplifier was proved and emitter capacitive peaking was used to remedy this problem. The tradeoff between the input impedance matching and bandwidth was also found.


international solid-state circuits conference | 2006

N

Chun-Kuang Chen; R.-Z. Hwang; Long-Sun Huang; Siou-Shen Lin; Hsiao-Chin Chen; Yu-Che Yang; Yu-Tso Lin; Shih-An Yu; Y.-H. Wang; Nai-Kuan Chou; Shey-Shi Lu

A quick (<30min.), label-free detection of disease-related C-reactive proteins (CRP) is achieved using a 200mum MEMS microcantilever housed in a 7times7mm2 reaction chamber. The deflection of the cantilever due to specific CRP/anti-CRP binding is detected using a position-sensitive photodiode and the converted bio-signal is transmitted by a wireless ASK transceiver IC fabricated in a 0.18mum CMOS process. CRP concentrations from 1mug/mL to 500mug/mL can be detected. A 0.2Hz 1V ac signal is applied to the bio-MEMS sensor to unbind CRP from the cantilever for reuse


international solid-state circuits conference | 2007

Frequency Synthesizers

Shih-An Yu; Peter R. Kinget

A 2.5GHz fractional-N synthesizer is realized in a digital 90nm CMOS technology. The RF dividers operate at 0.65V while the remainder of the PLL operates at 0.5V; no special devices or voltage boosting is used to achieve the 0.5V operation. The synthesizable range covers 2.4 to 2.6GHz with a phase noise of -55dBc/Hz in band and -120dBc/Hz at a 3MHz offset. The synthesizer dissipates 7mW and occupies 0.14mm2.


IEEE Microwave and Wireless Components Letters | 2005

A 0.65-V 2.5-GHz Fractional-N Synthesizer With Two-Point 2-Mb/s GFSK Data Modulation

Yu-Che Yang; Shih-An Yu; Tao Wang; Shey-Shi Lu

A divide-by-1/1.5 divider cell using a dual edge-trigger technique is proposed. Based on this divider cell, a dual-mode programmable divide-by-X circuit is demonstrated in 0.18-/spl mu/m CMOS technology, where X=P or P.5 in one mode and 2P or 2P+1 in the other mode with P=128-255. When operated in the divide-by-2P/2P+1 mode, this circuit outputs a signal with 50% duty cycle. Theoretically, P can be any arbitrary and programmable integer.


IEEE Transactions on Circuits and Systems Ii-express Briefs | 2009

Analysis, design, and optimization of InGaP-GaAs HBT matched-impedance wide-band amplifiers with multiple feedback loops

Shih-An Yu; Peter R. Kinget

We present an oscillator design method that reduces the area of LC oscillators in extremely scaled CMOS technologies by taking advantage of the high fT of the transistors. The oscillator is scaled to operate at a higher frequency and is followed by a fixed-ratio divider. It maintains the same power consumption and performance for a given wanted output frequency while occupying a much smaller area. In principle, by scaling up the oscillation frequency N times, a factor of 1/N 2 can be obtained in inductor area reduction. Simulated results show that with uniformly scaled inductors, the figure of merit (FoM) of the scaled oscillators at 1, 2, 4, and 8 GHz can be within a 1-dB difference, whereas the figure of merit normalized for area (FoMA) improves with the oscillation frequency.


IEEE Journal of Solid-state Circuits | 2011

A Wireless Bio-MEMS Sensor for C-Reactive Protein Detection Based on Nanomechanics

Shih-An Yu; Y. Baeyens; J. S. Weiner; Ut-Va Koc; Marta Rambaud; Fang-Ren Liao; Young-Kai Chen; Peter R. Kinget

We present a 4.4-mm2 single-chip synthesized signal source with 125 MHz to 32 GHz continuous frequency coverage with a minimum frequency step smaller than 10 Hz. The chip is fabricated in a 0.18-μm SiGe BiCMOS 1P6M technology. A core fractional-N synthesizer using a 20-MHz reference frequency has four LC-VCOs and a 4- to 8-GHz synthesizable range. Post-synthesis blocks extend the frequency coverage up to 32 GHz and down to 125 MHz through frequency multiplication and division. In different operation modes, the chip, including a balanced 50-ohm load driver, consumes from 284 to 498 mW. The phase noise performance achieves -117.6 dBc/Hz at 1-MHz offset from a 6-GHz output frequency and -83 dBc/Hz in-band noise. The integrated phase noise is -28 dBc and the absolute jitter is 1.05 psRMS at 6-GHz output. The jitter is maintained nearly constant (between 0.9 and 1.2 psRMS) across the whole output frequency range.


IEEE Journal of Solid-state Circuits | 2016

A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS

Te Hsuen Tzeng; Chun Yen Kuo; San Yuan Wang; Po Kai Huang; Yen-Ming Huang; Wei Che Hsieh; Yu Jie Huang; Po Hung Kuo; Shih-An Yu; Si-Chen Lee; Yufeng J. Tseng; Wei Cheng Tian; Shey-Shi Lu

With the help of micro-electromechanical systems (MEMS) and complementary metal-oxide-semiconductor (CMOS) technology, a portable micro gas chromatography (μGC) system for lung cancer associated volatile organic compounds (VOCs) detection is realized for the first time. The system is composed of an MEMS preconcentrator, an MEMS separation column, and a CMOS system-on-chip (SoC). The preconcentrator provides a concentration ratio of 2170. The separation column can separate more than seven types of lung cancer associated VOCs. The SoC is fabricated by a TSMC 0.35 μm 2P4M process including the CMOS VOCs detector, sensor calibration circuit, low-noise chopper instrumentation amplifier (IA), 10 bit analog to digital converter, and the microcontrol unit (MCU). Experimental results show that the system is able to detect seven types of lung cancer associated VOCs (acetone, 2-butanone, benzene, heptane, toluene, m-xylene, 1,3,5-trimethylbenzene). The concentration linearity is R2 = 0.985 and the detection sensitivity is up to 15 ppb with 1,3,5-trimethylbenzene.

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Shey-Shi Lu

National Taiwan University

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Yu-Che Yang

National Taiwan University

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Chinchun Meng

National Chiao Tung University

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Hsiao-Chin Chen

National Taiwan University of Science and Technology

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Ming-Chou Chiang

National Taiwan University

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