Pei-Yun Tsai

Efficient Implementation of QR Decomposition for Gigabit MIMO-OFDM Systems

This paper presents a VLSI architecture of QR decomposition for 4×4 MIMO-OFDM systems. A real-value decomposed MIMO system model is handled and thus the channel matrix to be processed is extended to the size of 8×8. Instead of direct factorization, a QR decomposition scheme by cascading one complex-value and one real-value Givens rotation stages is proposed, which can save 44% hardware complexity. Besides, the requirement of skewed inputs in the conventional QR-decomposition systolic array is eliminated and 36% of delay elements are removed. The real-value Givens rotation stage is also constructed in a form of a stacked triangular systolic array to match with the throughput of the complex-value one. Hardware sharing is considered to enhance the utilization. The proposed design is implemented in 0.18-μm CMOS technology with 152K gates. From measurement, the maximum operating frequency is 100 MHz. It generates QR decomposition results every four clock cycles and accomplishes continuous projection every clock cycle to support MIMO detection up to 2.4 Gb/s. The measured power consumption is 318.6 mW and 219.6 mW for QR decomposition and projection, respectively, at the highest operating frequency. From the comparison, our proposed design achieves the highest throughput with high efficiency.

Joint weighted least-squares estimation of carrier-frequency offset and timing offset for OFDM systems over multipath fading channels

This work presents an algorithm for joint estimation of carrier-frequency offset and timing offset for orthogonal frequency-division multiplexing (OFDM) systems in the tracking mode. The proposed weighted least-squares algorithm derives its estimates based on phase differences in the received pilot subcarrier signals between two symbols. Moreover, the optimal weights in two different channel conditions are derived. Both analysis and simulation show that the weighted least-squares algorithm can effectively and accurately estimate the carrier-frequency offset as well as the timing offset of OFDM signals in multipath fading channels.

Frequency-domain interpolation-based channel estimation in pilot-aided OFDM systems

We propose a novel frequency-domain interpolation algorithm for channel estimation in comb-type pilot-aided orthogonal frequency-division multiplexing (OFDM) systems. There exist two major types of pilot-aided OFDM channel estimation methods: time-domain and frequency-domain. We show that these two estimation methods have mathematical equivalence. The performance of these channel estimators mainly depends on how the channel impulse response (CIR) is reconstructed from the frequency-domain channel response sample at the pilot sub-carriers. By closely examining time-domain CIR characteristics, we propose a new frequency-domain interpolation-based algorithm that can overcome the limitation of conventional frequency-domain algorithms. Meanwhile, this new algorithm has the advantages of less latency and computation complexity when compared to time-domain approaches. Simulation results show that the proposed algorithm outperforms frequency-domain interpolation-based and time-domain algorithms in most cases.

A new cell search scheme in 3GPP long term evolution downlink, OFDMA systems

This paper presents a cell search procedure in 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) downlink systems. The proposed cell search procedure contains three steps. In the beginning, conventional mode detection, symbol timing detection and fractional carrier frequency offset (CFO) estimation methods are adopted so that frequency-domain signal processing can be performed subsequently. Secondly, a new joint detection method for integer carrier frequency offset and sector cell index information is proposed, which is shown to be capable of resisting symbol timing error. Finally, we also proposed a detection method for frame timing and cell identity (ID) group information without explicit channel estimates. Simulation results demonstrate that the proposed scheme with lower detection error probability is effective and robust compared with some conventional approaches.

A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling

This paper presents a generalized conflict-free memory addressing scheme for memory-based fast Fourier transform (FFT) processors with parallel arithmetic processing units made up of radix-2q multi-path delay commutator (MDC). The proposed addressing scheme considers the continuous-flow operation with minimum shared memory requirements. To improve throughput, parallel high-radix processing units are employed. We prove that the solution to non-conflict memory access satisfying the constraints of the continuous-flow, variable-size, higher-radix, and parallel-processing operations indeed exists. In addition, a rescheduling technique for twiddle-factor multiplication is developed to reduce hardware complexity and to enhance hardware efficiency. From the results, we can see that the proposed processor has high utilization and efficiency to support flexible configurability for various FFT sizes with fewer computation cycles than the conventional radix-2/radix-4 memory-based FFT processors.

Baseband Receiver Design for Wireless MIMO-OFDM Communications: Chiueh/Baseband Receiver Design for Wireless MIMO-OFDM Communications

The Second Edition of OFDM Baseband Receiver Design for Wirless Communications, this book expands on the earlier edition with enhanced coverage of MIMO techniques, additional baseband algorithms, and more IC design examples. The authors cover the full range of OFDM technology, from theories and algorithms to architectures and circuits.The book gives a concise yet comprehensive look at digital communication fundamentals before explaining signal processing algorithms in receivers. The authors give detailed treatment of hardware issues - from architecture to IC implementation.Links OFDM and MIMO theory with hardware implementationEnables the reader to transfer communication received concepts into hardware; design wireless receivers with acceptable implemntation loss; achieve low-power designsCovers the latest standards, such as DVB-T2, WiMax, LTE and LTE-AIncludes more baseband algorithms, like soft-decoding algorithms such as BCJR and SOVAExpanded treatment of channel models, detection algorithms and MIMO techniquesFeatures concrete design examples of WiMAX systems and cognitive radio apllications Companion website with lecture slides for instructorsBased on materials developed for a course in digital communication IC design, this book is ideal for graduate students and researchers in VLSI design, wireless communications, and communications signal processing. Practicing engineers working on algorithms or hardware for wireless communications devices will also find this to be a key reference.

Joint weighted least squares estimation of frequency and timing offset for OFDM systems over fading channels

This paper presents an algorithm for joint estimation of carrier frequency offset and timing frequency offset in orthogonal frequency division multiplexing (OFDM) systems. A weighted least squares algorithm based on a pilot-aided scheme is proposed. The algorithm operates near the Cramer-Rao bound in the variance of estimation errors. Simulations of several estimation algorithms in a multipath fading channel show that this algorithm provides the most accurate estimation in both the carrier frequency offset and the timing frequency offset.

A Low-Power Multicarrier-CDMA Downlink Baseband Receiver for Future Cellular Communication Systems

In this paper, design and implementation of a baseband receiver integrated circuit (IC) for a downlink multi-carrier code-division multiple access (MC-CDMA) system are presented. This MC-CDMA system aims to provide higher data transmission capacity than the current wide-band CDMA systems in mobile cellular communication environments. The proposed chip provides a robust tracking mechanism for synchronization errors and an accurate channel estimation strategy to overcome the challenge of outdoor fast-fading channels. Besides, low-power and low-complexity architecture design techniques are adopted to satisfy mobile receiver needs. Experimental results of the designed baseband receiver integrated circuit demonstrate its superior system performance and great reduction in power consumption. The chip was fabricated in a 0.18-mum CMOS technology with a core area of 2.6 mm times 2.6 mm. It can support up to 21.7-Mbps uncoded data rate in a 5-MHz bandwidth. When running at 5.76 MHz, its power consumption is as low as 9.9 mW from a supply voltage of 1.1 V.

High-throughput QR decomposition for MIMO detection in OFDM systems

In this paper, we aim to design and implement a high-throughput QR decomposition architecture for 4 × 4 MIMO signal detection problems. A real-value decomposed MIMO system model is handled and thus the channel matrix to be processed is extended to the size 8×8. Instead of direct factorization, we propose a QR decomposition scheme by cascading one complex-value and one real-value Givens rotation blocks, which can save 44% hardware complexity. The systolic array is adopted for hardware implementation to facilitate pipeline design. Then, the requirement of skewed inputs to the conventional complex-value QR-decomposition systolic array is improved and 37% of delay elements are removed. The real-value Givens rotation stage is implemented by a stacked triangular systolic array to match with the throughput of the complex-value one. We have implemented the proposed design in 0.18 μm CMOS technology with 152K gates. From post-layout simulations, the maximum operating frequency can achieve 90.09MHz. The proposed scheme not only reduces the hardware complexity, but also supports high throughput for MIMO-OFDM signal detection up to 2.16 Gbps under stationary channels.

A 4×4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps

In this paper, a VLSI architecture of a reduced-complexity K-best sphere decoder is designed, which aims to solve the 4 × 4 64-QAM multiple-input multiple-output (MIMO) signal detection problems in high-speed applications. We propose a fully-pipelined sorter, which can generate one result per clock cycle and thus greatly enhance the detection throughput. On the other hand, various K values are adopted at each layer to save the hardware complexity. The proposed design has been implemented in 0.18 Jim CMOS technology and has 366K gates. From post-layout simulation, this work achieves a detection rate of 1.5 Gbps at 62.5-MHz clock frequency.