Tzi-Dar Chiueh

Parallel architectures for 3-step hierarchical search block-matching algorithm

The paper describes fully pipelined parallel architectures for the 3-step hierarchical search block-matching algorithm, a fast motion estimation algorithm for video coding. The advantage of this algorithm was completely utilized by use of intelligent data arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also developed. Because of their low costs, high speeds, and low memory bandwidth requirements, the proposed 3-PE, 9-PE, and 27-PE architectures provide efficient solutions for real-time motion estimations required by video applications of various data rates, from low bit-rate video to HDTV systems. >

An efficient and simple VLSI tree architecture for motion estimation algorithms

A low-latency, high-throughput tree architecture is proposed. This architecture implements both the full-search block-matching algorithm and the three-step hierarchical search algorithm in motion estimation. Owing to the simple and modular properties, the proposed architecture is suitable for VLSI implementation. Furthermore, it can be decomposed into subtrees to reduce hardware cost and pin count. The memory interleaving and the pipeline interleaving are also employed to enhance memory bandwidth and to use the pipeline 100%. Theoretical calculations and simulation results are presented to show the attractive performance. >

One-dimensional full search motion estimation algorithm for video coding

A new hardware-oriented algorithm called the one-dimensional full search (1DFS) is presented for block-matching motion estimation in video compression. The simulation for this algorithm follows H.261 and MPEG international standards. In MPEG simulation, structures with 1-, 2- and 3-frame interpolation are compared. The performance of 1DFS is superior to that of other fast search algorithms. And it has more regular data flow, data reuse and less control overhead. It is an alternative for 2D full search block matching and achieves a good compromise between computational complexity and performance. With competent performance and reasonable computation complexity, the proposed method is more suitable for real-time hardware realization of a VLSI motion estimator for video applications. >

A Low-Power Digit-Based Reconfigurable FIR Filter

In this brief, we present a digit-reconfigurable finite-impulse response (FIR) filter architecture with a very fine granularity. It provides a flexible yet compact and low-power solution to FIR filters with a wide range of precision and tap length. Based on the proposed architecture, an 8-digit reconfigurable FIR filter chip is implemented in a single-poly quadruple-metal 0.35-mum CMOS technology. Measurement results show that the fabricated chip operates up to 86 MHz when the filter draws 16.5 mW of power from a 2.5-V power supply

A new block-matching criterion for motion estimation and its implementation

A novel and efficient block-matching motion estimation criterion called minimized maximum error (MiniMax) is considered. The proposed method can save hardware area about 15% with acceptable video performance. A chip which combines the MiniMax matching criterion and the one-dimensional full search algorithm is presented. The ASIC is motivated by the need of the intensive computational demand to perform motion estimation in real time. The proposed single chip can match the applications of H.261 and MPEG international standards. Chip cascading is allowed for larger searching range applications. >

Accuracy improvement and cost reduction of 3-step search block matching algorithm for video coding

Proposes three modifications on the 3-step hierarchical search for video coding: the multiple-candidate search that improves the estimation accuracy, a method of subsampling that reduces computation and input data amount, and an overlapping strategy to improve the accuracy of a large-area search. Experimental results show that combining these techniques provides high-speed and high-precision motion estimators with reduced on-chip buffers and lower input bandwidth requirements. >

Joint weighted least-squares estimation of carrier-frequency offset and timing offset for OFDM systems over multipath fading channels

This work presents an algorithm for joint estimation of carrier-frequency offset and timing offset for orthogonal frequency-division multiplexing (OFDM) systems in the tracking mode. The proposed weighted least-squares algorithm derives its estimates based on phase differences in the received pilot subcarrier signals between two symbols. Moreover, the optimal weights in two different channel conditions are derived. Both analysis and simulation show that the weighted least-squares algorithm can effectively and accurately estimate the carrier-frequency offset as well as the timing offset of OFDM signals in multipath fading channels.

Active cancellation system of acoustic noise in MR imaging

Introduces a new neural-network architecture for reducing the acoustic noise level in magnetic resonance (MR) imaging processes. The proposed neural network (NN) consists of two cascaded time-delay NNs (TDNNs). This NN is used as the predictor of a feedback active noise control (ANC) system for reducing acoustic noises. Experimental results with real MR noises show that the proposed system achieved an average noise power attenuation of 18.75 dB, which compares favorably with previous studies. Preliminary results also show that with the proposed ANC system installed, acoustic MR noises are greatly attenuated while verbal communication during MRI sessions Is not affected.

A 74.8 mW Soft-Output Detector IC for 8

In this paper, VLSI implementation of a configurable, soft-output MIMO detector is presented. The proposed chip can support up to 8 × 8 64-QAM spatial multiplexing MIMO communications, which surpasses all reported MIMO detector ICs in antenna number and modulation order. Moreover, this chip provides configurable antenna number from 2 × 2 up to 8 × 8 and modulation order from QPSK to 64-QAM. Its outputs include bit-wise log likelihood ratios (LLRs) and a candidate list, making it compatible with powerful soft-input channel decoders and iterative decoding system. The MIMO detector adopts a novel sphere decoding algorithm with high decoding efficiency and superior error rate performance, called modified best-first with fast descent (MBF-FD). Moreover, a low-power pipelined quad-dual-heap (quad-DEAP) circuit for efficient node pool management and several circuit techniques are implemented in this chip. When this chip is configured as 4 × 4 64-QAM and 8 × 8 64-QAM soft-output MIMO detectors, it achieves average throughputs of 431.8 Mbps and 428.8 Mbps with only 58.2 mW and 74.8 mW respective power consumption and reaches 10-5 coded bit error rate (BER) at signal-to-noise ratio (SNR) of 24.2 dB and 22.6 dB, respectively.

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Communication using a power line as a medium provides a convenient and inexpensive way for data transmission and control signaling in households. This paper introduces a power-line channel model as well as architecture of a spread-spectrum baseband transceiver IC for a power-line modem. The modulation and spreading scheme used in the proposed transceiver is mary biorthogonal keying (MBOK). This transceiver runs at a chipping rate of 256 KHz and provides 128-kb/s data rate. Simulation results and FPGA emulation verify the effectiveness of the architecture for household data communication.