Peng H. Ang

Video compression makes big gains

How new standards for video compression and new IC chips will change the worlds of computing, broadcasting, and communication is discussed. An explanation of how video compression works is given. The three digital video standards that have been proposed are described. They are the Joint Photographic Experts Group (JPEG) standard for still picture compression, the Consultative Committee on International Telephony and Telegraphy (CCITT) Recommendation H.261 for video teleconferencing, and the Moving Pictures Experts Group (MPEG) for full-motion compression on digital storage media. Some available chip sets are described, and the issue of design flexibility is considered.<<ETX>>

A high-performance full-motion video compression chip set

A seven-chip set which performs the functions associated with video and image compression algorithms, and CCITT H.261 in particular, has been designed, fabricated, and is fully functional. The major functions performed by the devices include motion estimation, DCT and IDCT, forward and inverse quantization, Huffman coding and decoding, BCH error correction, and loop filtering. The chips that perform the predictive and transform coding section of the algorithm operate with pixel rates up to 40 MHz. Array-based technologies of 1.5 and 1.0 mu m CMOS were used extensively to achieve a 28 man-month design time. Each die is less than 10 mm on a side. >

A video-rate JPEG chip set

A two-chip set has been designed, fabricated and is fully functional which performs the baseline JPEG image compression and decompression algorithm. The major functions of the devices include: DCT and IDCT, forward and inverse quantization, Huffman coding and decoding. The devices operate with pixel rates beyond 30 MHz at 70 degrees C and 4.75 V. Each die is less than 10 mm on a side and was implemented in a 1.0 µ CMOS cell-based technology to achieve a 9 man-month design time.

Generation of high speed CMOS multiplier-accumulators

The authors describe MAGGEN (multiplier-accumulator generator), a technology-independent generator for high-speed CMOS Wallace-tree-based multiplier-accumulators (MACs). MAGGEN generates optimized netlists and compact layouts for MACs. MAGGENs fast parallel MAC design is achieved through timing optimization routines. Compact layout, on the other hand, is achieved through prudent floorplanning, matched with placement optimization. MAGGEN is an integral tool set. In addition to netlist and layout, it generates all data files to allow the MACS to be used readily as megafunctions (netlist only) or megacells (netlist and layout) in larger designs.<<ETX>>

Yet another multiplier architecture

The VLSI multiplier architecture discussed makes advances over previous architectures in terms of layout density and flexibility in making speed/size tradeoffs. This multiplier design and a ripple adder were used in LSI Logics L64814 floating point processor for use in Sun Microsystems SPARC system architecture. The novel architectural design yielded a 56-by-56, 30 ns, nonpipelined, 4100 transistor/mm/sup 2/, semi-custom, multiplier-accumulator. However, the architectural concept is general and flexible enough to accommodate any size multiplier and allow tradeoffs between a given multipliers area and speed.<<ETX>>

A reconfigurable 64-tap transversal filter

A high-speed transversal filter processor with 64 8-bit multiplier accumulators using several innovative custom design techniques has been realized in 14-mm*14-mm silicon at 20-MHz speeds. The processor (L64240) can be configured as a one-dimensional filter for radar or as a two-dimensional filter for real-time image applications. The authors describe the internal architecture of the filter, its key components, and the critical concerns addressing the speed and size of the design.<<ETX>>

A 40 MHz programmable and reconfigurable filter processor

A programmable and reconfigurable filter processor comprising four 16*16 multiplier-accumulators is presented. The processor, fabricated in a 1.5- mu m 2-layer metal CMOS process, has been tested and is fully functional up to 40 MHz clock frequency. It can be programmed and reconfigured via an on-chip sequencer for a range of applications, including radar signal processing, image processing, discrete cosine transform, discrete Fourier transform, and other general inner product applications.<<ETX>>

The architectures and design of a 20-MHz real-time DSP

A set of four real-time 20-MHz digital signal processor (DSP) chips have been designed, fabricated, and tested. The chips include a 64-tap programmable FIR (finite-impulse response) filter, a 1024-tap binary filter and template matcher, a 64-tap rank-value filter, and an eight-line 512-pixel video-line delay. All of the circuits were implemented in a 1.5- mu m CMOS process and are fully functional with a 20-MHz clock rate.<<ETX>>

Design of a 20 MHz 64-tap transversal filter

The authors describe the architecture and design of a high-speed CMOS VLSI filter processor. The internal architecture of the design is pipelined to achieve a sustained 20-MHz data throughput rate. This translates into an effective computational rate of 1.2 billion multiplications (and a similar number of additions) per second. The chip is reconfigurable for one- and two-dimensional filtering, the total device count is 240000 transistors, and the die size is 1.4 cm*1.4 cm. Tap design, data-flow organization, and clock distribution are discussed.<<ETX>>

A methodology for quick turn-around of high performance DSP ASICS

An approach that has been successfully in the design of a family of high-performance digital signal processors is described. It offers the advantage of a short design cycle without sacrificing performance. The method relies on the availability of a well-characterized standard cell library, an accurate gate-level simulator, a behavioral simulator for architectural evaluations, and module generators for generic digital signal processing operators such as multipliers and adders. The method has the flexibility of being able to retarget the logic description into either an array-based, cell-based, or even full-custom physical implementation.<<ETX>>