Per Karlström

High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4

Since the invention of FPGAs, the increase in their size and performance has allowed designers to use FPGAs for more complex designs. FPGAs are generally good at bit manipulations and fixed point arithmetics but has a harder time coping with floating point arithmetics. In this paper we describe methods used to construct high performance floating point components in a Virtex-4. We have constructed a floating point adder/subtracter and multiplier which we then used to construct a complex radix-2 butterfly. Our adder/subtracter can operate at a frequency of 361 MHz in a Virtex-4SX35 (speed grade -12)

High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4

There is increasing interest about floating-point arithmetics in field programmable gate arrays (FPGAs) because of the increase in their size and performance. FPGAs are generally good at bit manipulations and fixed-point arithmetics, but they have a harder time coping with floating-point arithmetics. An architecture used to construct high-performance floating-point components in a Virtex-4 FPGA is described in detail. Floating-point adder/subtracter and multiplier units have been constructed. The adder/subtracter can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade -12).

NoGAP: A Micro Architecture Construction Framework

Flexible Application Specific Instruction set Processors (ASIP) are starting to replace monolithic ASICs in a vide variety of fields. However the design of an ASIP is today a substantial design effort. This paper discusses

A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA

{\ensuremath{\mathfrak{NoGap}}}

Operation Classification for Control Path Synthetization with NoGAP

(Novel Generator for ASIP) a tool for ASIP designs utilizing hardware multiplexed data paths. One of the main advantages of

NoGap CL : A flexible common language for processor hardware description

{\ensuremath{\mathfrak{NoGap}}}

Design of PIONEER: A case study using NoGap

compared to other ADL tools is that it does not impose limits on the architecture and thus design freedom. To reach this flexibility

Automatic port and bus sizing in NoGap

{\ensuremath{\mathfrak{NoGap}}}

Implementation of a Floating Point Adder and Subtracter in NoGAP, A Comparative Case Study

makes heavy use of the compositional design principle and is therefore divided into three parts

Design of SENIOR: A Case Study Using \mathfrak{NoGap}

\mathfrak{Mage}