Perry J. Robertson

A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond

The Sandia National Laboratories (SNL) Data Encryption Standard (DES) Application Specific Integrated Circuit (ASIC) is the fastest known implementation of the DES algorithm as defined in the Federal Information Processing Standards (FIPS) Publication 46-2. DES is used for protecting data by cryptographic means. The SNL DES ASIC, over 10 times faster than other currently available DES chips, is a high-speed, fully pipelined implementation offering encryption, decryption, unique key input, or algorithm bypassing on each clock cycle. Operating beyond 105 MHz on 64 bit words, this device is capable of data throughputs greater than 6.7 Billion bits per second (tester limited). Simulations predict proper operation up to 9.28 Billion bits per second. In low frequency, low data rate applications, the ASIC consumes less that one milliwatt of power. The device has features for passing control signals synchronized to throughput data. Three SNL DES ASICs may be easily cascaded to provide the much greater security of triple-key, triple-DES.

Development of a light-weight, wind-turbine-rotor-based data acquisition system

Wind-energy researchers at Sandia National Laboratories (SNL) and the National Renewable Energy Laboratory (NREL) are developing a new, light-weight, modular system capable of acquiring long-term, continuous time-series data from current-generation small or large, dynamic wind-turbine rotors. Meetings with wind-turbine research personnel at NREL and SNL resulted in a list of the major requirements that the system must meet. Initial attempts to locate a commercial system that could meet all of these requirements were not successful, but some commercially available data acquisition and radio/modem subsystems that met many of the requirements were identified. A time synchronization subsystem and a programmable logic device subsystem to integrate the functions of the data acquisition, the radio/modem, and the time synchronization subsystems and to communicate with the user have been developed at SNL. This paper presents the data system requirements, describes the four major subsystems comprising the system, summarizes the current status of the system, and presents the current plans for near-term development of hardware and software.

ATLAS - A small, light weight, time-synchronized wind-turbine data acquisition system

Wind energy researchers at Sandia National Laboratories have developed a small, lightweight, time- synchronized, robust data acquisition system to acquire long-term time-series data on a wind turbine rotor. A commercial data acquisition module is utilized to acquire data simultaneously from multip!e strain-gauge, analog, and digital channels. Acquisition of rotor data at precisely the same times as acquisition of ground data is ensured by slaving the acquisition clocks on the rotor- based data unit and ground-based units to the Global Positioning Satellite (GPS) system with commercial GPS receiver units and custom-built and programmed programmable logic devices. The acquisition clocks will remain synchronized within two microseconds indefinitely. Field tests have confirmed that synchronization can be maintained at rotation rates in excess of 350 rpm, Commercial spread-spectrum radio modems are used to transfer the rotor data to a ground- based computer concurrently with data acquisition, permitting continuous acquisition of data over a period of several hours, days or even weeks.

Protection of distributed internetworked computers

Current methods of enforcing security policy depend on security patches, anti-virus protections, and configuration control, all updated in the end users computer at ever decreasing intervals. This research is producing a method of hardening the corporate computer infrastructure by prototyping a mixed hardware and software architecture that enforces policies by pushing distributed security functions closer to the end users computer, but without modifying, relying on or reconfiguring the end users computer itself. Previous research has developed highly secure network components. Because it is impractical to replace our entire infrastructure with secure, trusted components, this paper investigates how to improve the security of a heterogeneous infrastructure composed of both trusted and untrusted components.

Preliminary systems engineering evaluations for the National Ecological Observatory Network.

The National Ecological Observatory Network (NEON) is an ambitious National Science Foundation sponsored project intended to accumulate and disseminate ecologically informative sensor data from sites among 20 distinct biomes found within the United States and Puerto Rico over a period of at least 30 years. These data are expected to provide valuable insights into the ecological impacts of climate change, land-use change, and invasive species in these various biomes, and thereby provide a scientific foundation for the decisions of future national, regional, and local policy makers. NEONs objectives are of substantial national and international importance, yet they must be achieved with limited resources. Sandia National Laboratories was therefore contracted to examine four areas of significant systems engineering concern; specifically, alternatives to commercial electrical utility power for remote operations, approaches to data acquisition and local data handling, protocols for secure long-distance data transmission, and processes and procedures for the introduction of new instruments and continuous improvement of the sensor network. The results of these preliminary systems engineering evaluations are presented, with a series of recommendations intended to optimize the efficiency and probability of long-term success for the NEON enterprise.

Data encryption standard ASIC design and development report.

This document describes the design, fabrication, and testing of the SNL Data Encryption Standard (DES) ASIC. This device was fabricated in Sandias Microelectronics Development Laboratory using 0.6 {micro}m CMOS technology. The SNL DES ASIC was modeled using VHDL, then simulated, and synthesized using Synopsys, Inc. software and finally IC layout was performed using Compass Design Automations CAE tools. IC testing was performed by Sandias Microelectronic Validation Department using a HP 82000 computer aided test system. The device is a single integrated circuit, pipelined realization of DES encryption and decryption capable of throughputs greater than 6.5 Gb/s. Several enhancements accommodate ATM or IP network operation and performance scaling. This design is the latest step in the evolution of DES modules.

Final Report and Documentation for the Optical Backplane/Interconnect for High Speed Communication LDRD

Current copper backplane technology has reached the technical limits of clock speed and width for systems requiring multiple boards. Currently, bus technology such as VME and PCI (types of buses) will face severe limitations are the bus speed approaches 100 MHz. At this speed, the physical length limit of an unterminated bus is barely three inches. Terminating the bus enables much higher clock rates but at drastically higher power cost. Sandia has developed high bandwidth parallel optical interconnects that can provide over 40 Gbps throughput between circuit boards in a system. Based on Sandias unique VCSEL (Vertical Cavity Surface Emitting Laser) technology, these devices are compatible with CMOS (Complementary Metal Oxide Semiconductor) chips and have single channel bandwidth in excess of 20 GHz. In this project, we are researching the use of this interconnect scheme as the physical layer of a greater ATM (Asynchronous Transfer Mode) based backplane. There are several advantages to this technology including small board space, lower power and non-contact communication. This technology is also easily expandable to meet future bandwidth requirements in excess of 160 Gbps sometimes referred to as UTOPIA 6. ATM over optical backplane will enable automatic switching of wide high-speed circuits between boards in a system. In the first year we developed integrated VCSELs and receivers, identified fiber ribbon based interconnect scheme and a high level architecture. In the second year, we implemented the physical layer in the form of a PCI computer peripheral card. A description of future work including super computer networking deployment and protocol processing is included.

Final Report for the 10 to 100 Gigabit/Second Networking Laboratory Directed Research and Development Project

The next major performance plateau for high-speed, long-haul networks is at 10 Gbps. Data visualization, high performance network storage, and Massively Parallel Processing (MPP) demand these (and higher) communication rates. MPP-to-MPP distributed processing applications and MPP-to-Network File Store applications already require single conversation communication rates in the range of 10 to 100 Gbps. MPP-to-Visualization Station applications can already utilize communication rates in the 1 to 10 Gbps range. This LDRD project examined some of the building blocks necessary for developing a 10 to 100 Gbps computer network architecture. These included technology areas such as, OS Bypass, Dense Wavelength Division Multiplexing (DWDM), IP switching and routing, Optical Amplifiers, Inverse Multiplexing of ATM, data encryption, and data compression; standards bodies activities in the ATM Forum and the Optical Internetworking Forum (OIF); and proof-of-principle laboratory prototypes. This work has not only advanced the body of knowledge in the aforementioned areas, but has generally facilitated the rapid maturation of high-speed networking and communication technology by: (1) participating in the development of pertinent standards, and (2) by promoting informal (and formal) collaboration with industrial developers of high speed communication equipment.