Peter Brooker

Analysis of topography effects on lithographic performance in double patterning applications

Double Patterning (DP) is considered the most viable solution for printing features of the 32nm technology node using 193nm immersion lithography. Independent of the approach of the DP implementation (be it Litho-Etch-Litho-Etch or Litho-Process-Litho-Etch), the second lithography step is influenced by the underlying topography on the wafer. Given the tight constraints on the process, an accurate prediction of the impact of the embedded topography on critical features is inevitable to meet the design requirements of the corresponding device layer. In this paper we use rigorous simulations of the electro-magnetic field distribution to quantify the effect of wafer topography on the second lithography step. In particular, we investigate the impact of the topography on CD control and corresponding process windows for typical 1D patterns. The influence of non-flat BARC, non-flat resist surfaces, hard mask material and process variations in the first litho step is simulated for dual line as well as dual trench processes. A metric to quantify standing waves in resist is introduced and used to optimize BARC thickness. Further, we investigate typical 2D clips of decomposed mask layouts relevant for the 32nm node. The simulation methodology and algorithm performance are presented, in particular with respect to its distributed computing capabilities.

Quantification of electron-beam proximity effects using a virtual direct write environment

An e-beam exposure module has been developed for an existing lithography simulator, covering aspects of e-beam inter-action with the stack, exposure of the resist by the e-beam as well as development of the resist. The goal of the simulation is to complement experimental data with insights that are difficult or impossible to obtain experimentally and to provide advanced capabilities for process optimization. Simulations are performed for an iso-dense pattern to show that in the case of 5kV acceleration voltage, a standard dose correction works well for tight beams with 5nm blur but is very challenging for 30nm beam blur. Geometric corrections will most likely be needed for a wide beam blur.

Efficient full-chip mask 3D model for off-axis illumination

Mask topography (Mask3D) effect is one of the most influential factors in sub-28 nm technology node. To build a successful Mask3D compact model, the runtime efficiency, accuracy and the flexibility to handle various geometry patterns are the three most important criterion to fulfill. In the meanwhile, Mask3D modeling must be able to handle the off-axis illumination (OAI) condition accurately. In this paper, we propose our full chip Mask3D modeling method which is an extension to the edge-based Mask3D model. In our modeling flow, we first review the edge-based Mask3D model and then analyze the impact from the off-axis source. We propose a parameter-based extension to characterize the off-axis impact efficiently. We further introduce two methods to calibrate the OAI-aware parameters by using rigorous or wafer data as the reference. Our experimental results show the great calibration accuracy throughout the defocus range with OAI sources, and validate the accuracy of our two parameter calibration approach.

7nm node EUV predictive study of mask LER transference to wafer

The transition into smaller nodes has resulted in stringent CD tolerance requirements and the role of mask LER in that budget is not sufficiently understood. The critical variables associated with mask LER were explored with the goal of establishing mask requirements based on wafer requirements. A systematic study of the impact of mask LER correlation length (ξ), critical exponent (α) and standard deviation of the line edge (σ) on the printability of 7nm node line/space (L/S) and contact holes (CH) in extreme ultraviolet lithography has been simulated. An experimentally relevant range of the three mask LER variables was explored in these simulations. CDU and CER/LER were the primary metrics used to gauge printability and they were evaluated as a function of ξ, α and σ with stochastic simulations. A 45nm pitch was investigated to determine critical mask LER parameters that mark printability transition regions relevant to the 7nm node middle of line.

Design-based metrology for development and manufacturing applications

This work presents how the combination of EDA and CDSEM tools enable development and manufacturing engineers to collect CDSEM data of a large diversity of features and contexts seamlessly for OPC model calibration and validation, process development, and inline manufacturing monitoring. We will present the application and results of a solution proposed in a previously published paper[1] and then review the benefits of enabling development and manufacturing engineers to make metrology-related decisions within their environments. Finally, new applications for automated CDSEM recipe generation and data collection will be discussed.

Automated SEM recipe generation for OPC applications

This work presents software tools that enable engineers to make relevant SEM measurement decisions in the EDA environment, presented in the optimal context for the engineer, and pass them seamlessly into the SEM environment. We present the tools and interfaces leveraged in this solution and explore the benefits of enabling OPC modeling engineers to make metrology-related decisions within the OPC environment. New opportunities for automation of metrologyrelated OPC tasks are also discussed.

Integrated advanced hotspot analysis techniques in the post-OPC verification flow

Improvements in compact lithography models and compute resources have allowed EDA suppliers to keep up with the accuracy and turnaround time (TAT) requirements for each new technology node. Compact lithography models are derived from the Hopkins method to calculate the image at the wafer. They consist of the pre-calculated optical kernel set that includes properties of projection and source optics as well as resist effects. The image at the wafer is formed by the convolution of optical kernel set with the mask transmission. The compact model is used for optical proximity correction (OPC) and lithography rule checking (LRC) due to its excellent turnaround time in full chip applications. Leading edge technology nodes, however, are inherently more sensitive to process variation and typically contain more low contrast areas, sometimes resulting in marginal hotspots. In these localized areas, it is desirable to have access to more predictive first principle lithography simulation. The Abbe method for lithography simulation includes full 3D resist models that solves from first principles the reaction/diffusion equation of the post exposure bake to provide the highest accuracy. These rigorous models have the ability to provide added insight into 3D developed profile in resist at the wafer level to assist in the application of OPC and disposition of hotspots found by LRC using compact models. This paper will explore the benefits of a tightly integrated rigorous lithography simulation during LRC hotspot detection step of the post OPC flow. Multiple user flows will be addressed along with methods for automating the flows to maximize the imaging predictability where needed while keeping the impact to turn around time to a minimum.

Metrology data cleaning and statistical assessment flow for modeling applications

Modern OPC modeling relies on substantial volumes of metrology data to meet pattern coverage and precision requirements. This data must be reviewed and cleaned prior to model calibration to prevent bad data from adversely affecting calibration. We propose implementing specific tools in the metrology flow to improve metrology engineering efficiency and resulting data quality. The metrology flow with and without these tools will be discussed, and the inherent tradeoffs will be identified. To demonstrate the benefit of the proposed flow, engineering efficiency and the impact of better data on model calibration will be quantified.

Application of photolithographic simulation and a mask repair system in a production environment

This work represents one in a series of ongoing papers demonstrating the potential utility of integrating advanced photolithographic simulation software into a mask repair tool to provide immediate defect or repair printability feedback. The equipment used here is an AFM-technology based nanomachining photomask repair tool where the high-accuracy AFM surface topography data is fed directly into software applying rigorous solutions to Maxwells equations. The nature of these systems allows for process endpoint printability evaluation, not restricted by the optical limitations of any given apparatus, of any micro to nano-scale region of the mask in-situ with the defect repair process. In prior work, the capability of this approach was shown in good correlations to AIMSTM at 248 and 193 nm wavelengths, for binary mask repairs of varying dimensions, with no applied optical aberrations to the simulation. In this examination, the development of this system is taken to its next step by introducing it to a real photomask production environment, using production masks, for performance substantiation. Methodologies are shown for the best use of this system in streamlining the mask production process.

Impact of AFM scan artifacts on photolithographic simulation

This work represents one in a series of ongoing papers demonstrating the potential utility of integrating advanced photolithographic simulation software into a mask repair tool to provide immediate defect or repair printability feedback. The equipment used here is an AFM-technology based nanomachining photomask repair tool where the high-accuracy AFM surface topography data is fed directly into software applying rigorous solutions to Maxwells equations. The nature of these systems allows for process endpoint printability evaluation, not restricted by the optical limitations of any given apparatus, of any micro to nano-scale region of the mask concurrent with the normal defect repair process. However, known AFM scan artifacts can impact the accuracy and stability of the photolithographic simulation results, especially for mask or pattern types which have not been previously studied by the user. The relevant sources of these artifacts are identified and improvements in the AFM operation are discussed which could minimize them. The quantitative relationships between the various artifact measures and their corresponding effects on various simulation results (including relative transmission and CD) are examined for both AIMSTM aerial imaging and wafer print. From this examination, error baselines are established and software, as well as model setup, optimizations are proposed.