Peter Elenius

Ultra CSP/sup TM/-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP/sup TM/. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed.

Flip chip reliability: comparative characterization of lead free (Sn/Ag/Cu) and 63Sn/Pb eutectic solder

The reliability of a ternary Sn/Ag/Cu alloy for flip chip solder joints will be reported in this paper. Dominant failure mechanisms for given thermal stress regimes are well defined for 63Sn/Pb eutectic solder. Characterizing Sn/Ag/Cu solder reliability in comparison to 63Sn/Pb solder provides a true baseline for these thermal stress regimes and still allows for a broad search of mechanisms due to the change in alloy properties inherent in this new metallurgic system. Reliability characterization must examine both solder bump and under bump metallization (UBM) robustness, because the interaction between the two contributes to the overall efficacy of the structure. Reported in this work are thermal cycle, high temperature storage, and die shear test results demonstrating the solder bump reliability. Electromigration, multiple reflow, and bare die high temperature test results verifying the UBM robustness are also presented. In addition, the assembly-related details are reported in an effort to provide a foundation for improved yield.

Solder joint reliability of a polymer reinforced wafer level package

Abstract Wafer level packages (WLPs) have demonstrated a very clear cost-advantage vs traditional wire-bond technologies, especially for small components that have a high number of dice and I/O per wafer. Ultra CSP® is a WLP developed by the Kulicke & Soffa Flip Chip Division (formally Flip Chip Technologies). Typical products utilizing the Ultra chip scale package (CSP) have 5×5 or less area arrays at 0.5 mm pitch. This relatively small array has been limited by the inherent solder joint reliability of WLPs. A much larger subset of higher I/O IC’s could benefit from WLPs provided that standard reliability requirements are achieved without the use of underfill. A new polymer reinforcement technology, “Polymer Collar WLP™”, has been developed by K&S Flip Chip Division. Polymer Collar WLP utilizes a polymer reinforcement structure surrounding the solder joint and it has demonstrated more than 50% increase in solder joint life in thermal cycling tests. The most attractive feature of the Polymer Collar WLP process is its simplicity. A simple replacement of the standard solder flux with Polymer Collar material during the solder attach process is all that is required. This simplicity makes Polymer Collar the most cost-effective solution for adding a polymer reinforcement structure to the solder joint. Other methods in use today require additional complex and costly manufacturing steps. This Polymer Collar WLP is expected to widen the WLP market to include larger arrays where the Ultra CSP did not have suitable solder joint reliability.

Deformation and crack growth characteristics of SnAgCu vs 63Sn/Pb solder joints on a WLP in thermal cycle testing

SAC (SnAgCu) lead free solder is currently the alloy of choice by the electronics industry for lead free applications. In this study multiple WLPs (Wafer Level Packages) called the Ultra CSP/sup TM/ from Flip Chip Technologies were put into a TC (Thermal Cycling) test. The goal was to see if the current AI/NiV/Cu UBM (Under Bump Metallurgy) system that has been used for eutectic SnPb solder Ultra CSP would be suitable for the SAC lead free solder version. Both SAC and eutectic SnPb solders were tested together. In this TC test, two parts were taken out of the TC chamber after every 200 cycles for monitoring the characteristics of deformation and crack growth in the solder joints. The result showed eutectic SnPb solder joints might have a global and uniform deformation in the high temperature regime. On the other hand, in the low temperature regime, the deformation is localized only at chip side solder joint while maintaining the global deformed shape from the previous high temperature regime. This localized deformation at low temperature regime created a large shear dislocation at chip side solder joint, with the crack initiating at the outside corner of the solder joint and growing toward the inside of chip. On the other hand, the SAC solder joints did not show that kind of large sliding at chip side solder joint. Instead two cracks initiated at both the outside and inside of chip side solder joint and grew at almost the same rate. There was very good agreement between Weibull life and the time that the cracked length (%) goes to 100% in eutectic SnPb solder. Extending this correlation to SAC lead free solder appears to be possible. Indications are that there will be an improvement, but there was insufficient data to make a conclusive statement as to reliability improvement. Tests are underway to confirm this.

Reliability characterization in Ultra CSP/sup TM/ package development

Ultra CSP/sup TM/ is a wafer-level chip scale package developed by Flip Chip Technologies. This package provides a low cost packaging solution for various applications such as integrated passive, flash memory, DRAM, and Direct RDRAM/sup TM/ devices. This paper presents a brief update of the Ultra CSP development effort. Two design concepts were evolved in the development process and product implementation to address the requirements of different applications. Solder joint reliability of Ultra CSP was evaluated at board level under thermal cycle test. A solder joint fatigue database was generated using Weibull analysis. The effect of die size (DNP), bump standoff, substrate pad size, and solder ball size are discussed. Continued improvement in the package reliability is achieved through Design of Experiments. Issues encountered in the qualification stage are addressed in terms of accelerated test strategy, process quality control, package design, and substrate design.