Young-Do Kweon

Reliability characterization in Ultra CSP/sup TM/ package development

Ultra CSP/sup TM/ is a wafer-level chip scale package developed by Flip Chip Technologies. This package provides a low cost packaging solution for various applications such as integrated passive, flash memory, DRAM, and Direct RDRAM/sup TM/ devices. This paper presents a brief update of the Ultra CSP development effort. Two design concepts were evolved in the development process and product implementation to address the requirements of different applications. Solder joint reliability of Ultra CSP was evaluated at board level under thermal cycle test. A solder joint fatigue database was generated using Weibull analysis. The effect of die size (DNP), bump standoff, substrate pad size, and solder ball size are discussed. Continued improvement in the package reliability is achieved through Design of Experiments. Issues encountered in the qualification stage are addressed in terms of accelerated test strategy, process quality control, package design, and substrate design.

Advanced high density interconnection substrate for mobile platform application

The faster market trend towards smart phones with more advanced computing ability and connectivity will drive the greater need to incorporate more functionality in smaller space by integrating more components and functional blocks into convergent systems in form of chip-level (SOC) or die-level (SIP) packaging. As feature size continues to shrink, it requires combination of stringent design requirements which all interact in order to achieve the desired performance. Also, various limitations will arise in the design of the PCB in terms of size and signal integrity. The substrate or PCB plays critical role in the miniaturization of the overall system and the final applications electrical performance. Given the extreme routing requirement of each component package with high I/O pins and fine pitch area array, the conventional HDI substrate pose some design challenges and limitations. In order to increase the routing density, it often requires smaller trace width and micro via diameter and even the need of adding more metal layers. These, however, will dramatically increase the cost and more reliability risk is expected. In this paper, we present a new generation substrate that could meet the mobile platform requirement by proposing an advanced ultra fine metal resolution substrate. It will demonstrate its high density interconnect capability in a basic 4-layer stack-up structure. One of its advanced features is the ability to adjust board and interconnection impedance in order to optimize signal integrity and more routing capability for dense mobile platform layouts. It will also demonstrate that organic-based substrate may also achieve tighter routing density using limited number of metal layers at smaller and thinner form factor while maintaining the desired signal integrity performance as compared to conventional 8-layer or 10-layer HDI PCBs. Details of electrical simulation and measurement of electrical parameters are also presented and discussed.

Bumpless Ball Grid Array (BBGA) package using a solder resist cavity

In this study, the package named Bumpless Ball Grid Array (BBGA) was developed. In BBGA package, chips were buried in the cavities made with solder resist materials. For BBGA package development, epoxy based photo-patternable solder resist was used as an encapsulation material because of cost effectiveness and process simplicity. This solder resist film was laminated on the Cu plate and cavities were formed by a lithography method. After the cavity formation, chips were buried in these cavities, and then dielectric layer was applied on the solder resist and the chip surface.

Dual chip memory package

Todays computer systems require more main memories than before due to the development of heavy-load softwares and the integration of multiple functions in a computer. However, since the computers became portable the sizes of computers are getting smaller. This means that it is necessary to put more memory chips into a limited space of the computers. In order to fulfil above requirement, a new high density package was developed, which looked the same as conventional plastic packages outside, and contained two chips inside, and named the Dual Chip Package (DCP). In packaging two chips in a package outline, chip-on-tape (COT) technology was combined with lead frames. The tape had wiring patterns inside and interconnection tabs along the periphery of the tape. The lead frames for the DCP were prepared by bonding the inner leads of the lead frames to the interconnection tabs of the tapes. Two chips are attached to the top side and the bottom side of the tape, and wire-bonded onto the tape surface. In the chip attachment and wire bonding process, one side of the tape was coated with an epoxy encapsulant to protect the chips during the wire bonding of the other side. After this process, the assembly processes were the same as those of conventional plastic packages. With DCP, it is possible to change the pin configurations of the package by varying the design of the tape. Reliability tests showed that the DCP met JEDEC level 3 requirement in pre-conditioning tests.

Wafer Level SAW RF Filter Packaging With Through Wafer Via Interconnection

This study describes the wafer level 0.8x0.6 mm2 SAW filter (Surface Acoustic Wave Filter) with interconnection via and LiTaO3 (LT)-LiTaO3 (LT) wafer bonding structure. The via formation for interconnection is based on smaller package manufacture. The interconnection via is made by blind via and wafer thinning process. The blind via is formed by sand blasting process or laser drilling process. The eutectic bonding is applied to LT and LT bonding with Au-Sn for device protection and pads interconnection. These processes enable the wafer level saw filter. The result of electrical performance and laser process and sandblaster process for wafer level SAW filter package is discussed