Peter Feldmann

Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals

In the process of designing state-of-the art VLSI circuit we often encounter large but highly structured linear subcircuits with large number of terminals. Classical examples are power supply networks, clock distribution networks, large data buses, etc. Various applications would benefit from efficient high level models of such networks. Unfortunately the existing model-order-reduction algorithms are not adapted to handle more than a few tens of terminals. This talk introduces RecMOR, an algorithm for the computation of reduced order models of structured linear circuits with numerous I/O ports. The algorithm exploits certain regularities of the subcircuit response that are typical in numerous applications of interest. When these regularities are present, the normally dense matrix-transfer function of the subcircuit contains sub-blocks that in some sense are significantly low rank and can be compactly modeled by the recently introduced SVDMOR algorithm. The new RecMOR algorithm decomposes the large matrix-transfer function recursively, and applies SVDMOR compression adaptively to the sub-blocks of the transfer function. The result is a reduced order model that is sparse, efficient, and directly usable as an efficient substitute of the subcircuit in circuit simulations. The method is illustrated on several circuit examples.

Model order reduction techniques for linear systems with large numbers of terminals

This paper addresses the well known difficulty of applying model order reduction (MOR) to linear circuits with a large number of input-output terminals. Traditional MOR techniques substitute the original large but sparse matrices used in the mathematical modeling of linear circuits by models that approximate the behavior of the circuit at its terminals, and use significantly smaller matrices. Unfortunately these small MOR matrices become dense as the number of terminals increases, thus canceling the benefits of size reduction. The paper introduces a model reduction technique suitable for circuits with numerous terminals. The technique exploits the correlation that almost always exists between circuit responses at different terminals. The correlation is rendered explicit through an SVD-based algorithm and the result is a substantial sparsification of the MOR matrices. The proposed sparsification technique is applicable to a large class of problems encountered in the analysis and design of interconnect in VLSI circuits. Relevant examples are used to analyze and validate the method.

Driver waveform computation for timing analysis with multiple voltage threshold driver models

This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs formalize a class of gate models which include the existing industry standards, such as CCS and ECSM driver models as special cases. The analysis technique relies on primary MVTM characterization data and does not require explicit instantiation of controlled current source models. Therefore, the method is more accurate, efficient, and general than traditional transient analysis. The theoretical results are validated by detailed simulations and use within full chip timing analysis.

Towards a more physical approach to gate modeling for timing, noise, and power

Timing, noise, and power analysis have historically relied on high level, black-box, non-physical logic library models. Moreover, these models were of a look-up type, i.e. pre- characterized for practically all the possible environments in which they would be eventually used. The evolution of the VLSI technology towards nanometer sized features made this characterization methodology impractical. Increasingly, the space of all possible environments grew too rich to be fully covered during characterization. In the past decade, the so-called effective capacitance was introduced to provide some analysis capability to gate models, i.e., the ability to evaluate in the presence of RC loads, although characterized with capacitive loads only. In current and future VLSI technologies, such simple extensions no longer provide the required accuracy. Increasingly, models of logic gates must retain elements of the electrical behavior of the circuit in order to provide accurate timing, noise, and power information. This poses a new challenge on the analysis algorithms, now required to handle an enhanced level of detail in modeling without significantly degrading the overall efficiency of the application.

A moment-based effective characterization waveform for static timing analysis

Static timing analysis of VLSI circuits relies on tabular models of logic gates obtained during library characterization. At characterization time logic gates are simulated at the circuit level with a range of input waveforms (e.g., saturated ramps with different slews) and various output loads. At timing analysis time the same gates are driven by input waveforms that differ from the class of characterization waveforms. This paper proposes a method for mapping the waveforms that arise in static timing analysis to members of the class of waveforms used to characterize gate timing performance during library characterization. The method is based on the moments of the input waveform, which describe concisely the salient features of the waveform. The mapping between the input waveform and the effective characterization waveform is accomplished by positing functional relationships between the input waveforms moments and the parameters of the characterization waveform. The unknown coefficients of this functional relationship are determined by minimizing the worst case error of the output waveform over a representative set of input waveforms and gate loads. The technique requires no change to the library characterization procedure, and minimal change to the static timing tool with little to no additional computational burden on the timer.

Applications of Homotopy for solving AC Power Flow and AC Optimal Power Flow

This paper introduces a new paradigm for solving AC Power Flow (ACPF) and AC Optimal Power Flow (ACOPF) with improved convergence robustness. This approach exploits the globally convergent properties of continuation methods. Continuation methods achieve robustness by generating a sequence of nonlinear problems and repeatedly and consistently providing good initial guesses for locally convergent nonlinear solvers such as Newton-Raphson. The Homotopy implemented in this paper, (referred to as Power Flow Homotopy, PFH), is formulated in a way that gradually transforms the “easy” DC into the “difficult” AC Power Flow. Successive changes of the homotopy parameter modify the system of equations from fully linear and convex DC into non-linear and non-convex AC (optimal) power flow. As a result, the AC solution is obtained with increased robustness and multiple AC power flow solutions can also be detected. Similarly, Optimal Power Flow Homotopy (OPFH) is defined for solving AC Optimal Power Flow, by gradually transforming the convex DC OPF problem. Simulation results provide a comparison between the simple Newton-Raphson method and PFH in terms of performance and quality of detected solution. Comparisons are also performed between the Interior-Point method and OPFH.

MAISE: An Interconnect Simulation Engine for Timing and Noise Analysis

This paper describes MAISE, an embedded linear circuit simulator for use mainly within timing and noise analysis tools. MAISE achieves the fastest possible analysis performance over a wide range of circuit sizes and topologies by an adaptive architecture that allows applying the most efficient combination of model reduction algorithms and linear solvers for each class of circuits. The main pillar of adaptability in MAISE is a novel nodal-analysis formulation (PNA) which permits the use of symmetric, positive-definite Cholesky solvers for all circuit topologies. Moreover, frequently occurring special cases, e.g., inductor-resistor tree structures result in particular types of matrices that are solved by an even faster linear time algorithm. Model order reduction algorithms employed in MAISE exploit symmetry and positive-definiteness whenever available and use symmetric-Lanczos iteration and nonstandard inner-products for generating the Krylov subspace basis. The efficiency of the new simulator is supported by a wide range of industrial examples.

Efficient compression and handling of current source model library waveforms

This paper describes a waveform compression technique suitable for the efficient utilization, storage and interchange of the emerging current source model (CSM) based cell libraries. The technique is based on pre-processing of a collection of voltage/current waveforms for the cells in the library and then, constructing an orthogonal time-voltage/time-current waveform basis using singular-value decomposition. Compression is achieved by representing all waveforms as linear combination coefficients of adaptive subset of the basis waveforms. Experimental results indicate that adaptive waveform representation results in higher compression ratios than the waveform representation as a function of fixed set of basis functions. Interpolation and further compression are obtained by representing the coefficients as simple functions of various parameters, e.g., input slew, load capacitance, supply voltage, and temperature. The methods introduced in this paper are tested and validated on several industrial strength libraries, with spectacular compression results.

Homotopy Method for Finding the Steady States of Oscillators

Shooting, finite difference, or harmonic balance techniques in conjunction with a damped Newton method are widely employed for the numerical calculation of limit cycles of (free-running, autonomous) oscillators. In some cases, however, nonconvergence occurs when the initial estimate of the solution is not close enough to the exact one. Generally, the higher the quality factor of the oscillator the tighter are the constraints for the initial estimate. A 2-D homotopy method is presented in this paper that overcomes this problem. The resulting linear set of equations is underdetermined, leading to a nullspace of rank two. This underdetermined system is solved in a least squares sense for which a rigorous mathematical basis can be derived. An efficient algorithm for solving the least squares problem is derived where sparse matrix techniques can be used. As continuation methods are only employed for obtaining a sufficient initial guess of the limit cycle, a coarse grid discretization is sufficient to make the method runtime efficient.

Pure nodal analysis for efficient on-chip interconnect model order reduction

This paper described a model-order reduction (MOR) method based on a novel pure-nodal analysis formulation (PNA) which permits the use of symmetric, positive-definite Cholesky solvers for all circuit topologies. Moreover, frequently occurring special cases, e.g., inductor-resistor tree structures result in particular types of matrices that are solved by an even faster linear time algorithm. The model order reduction algorithms also uses symmetric-Lanczos iteration and non- standard inner-products for generating the Krylov subspace basis. Its efficiency is supported by a wide range of industrial examples.