Péter G. Szabó

Thermal Measurement and Modeling of Multi-Die Packages

Thermal measurement and modeling of multi-die packages with vertical (stacked) and lateral arrangement became a hot topic recently in different fields like RAM chip packaging or LEDs and LED assemblies. In our present study, we present results for a more complex structure: an opto-coupler device with four chips in a combined lateral and vertical arrangement. The paper gives an overview of measurement and modeling techniques and results for stacked and multichip module (MCM) structures. It describes actual measurement results along with our structure function-based methodology which helps validating the detailed model of the package being studied. For stack-die packages, we suggest an extension of the DELPHI model topology. Also, we show how one can derive junction-to-pin thermal resistances with a technique using structure functions.

Improved thermal characterization method of integrated microscale heat sinks

The thermal management of semiconductor devices is still a hot topic. Most designers, who are aware of the thermal aspects of IC design, know that new, cheaper and more efficient methods are required to keep the temperature of electronic systems low. Research by different teams regarding the cooling of stacked die structures is in progress.In this paper an improved thermal characterization method will be presented to determine the flow dependent partial thermal resistance of integrated microchannel based heat sinks. This reliable characterization method does not demand thermal isolation during the measurements, only constant environment conditions. The measurements are based on the industrial standard thermal transient testing method.On the other hand we present an approach to realize an integrated microfluidic channel based heat sink, which can be realized in the backside of the silicon chip itself. The approach is based on a cheap wet etching process instead of reactive ion etching or LIGA technologies, which enables batch processing.

DELPHI Style Compact Modeling of Stacked Die Packages

Multi-die packages with vertical (stacked) arrangement became popular in many application fields, necessitating appropriate thermal measurement and modeling techniques. In this study we present our attempt to yield boundary condition independent models of stacked die packages that reflect phenomena experienced by measurements. In our approach we propose an extension of the DELPHI model topology (accounting for multiple junctions). We also tried to extract most of the input data for model generation directly from thermal transient measurement results by the application of structure functions and by using electronically variable thermal resistances applied as boundary conditions during tests.

Short time die attach characterization of semiconductor devices

Thermal qualification of the die attach of semiconductor devices is a very important element in the device characterization as the temperature of the chip is strongly affected by the quality of the die attach. Voids or delaminations in this layer may cause higher temperature elevation and thus damage or shorter lifetime. Thermal test of each device in the manufacturing process would be the best solution for eliminating the devices with wrong die attach layer. In this paper we will present the short time thermal transient measurement method and the structure function evaluation through simulations and measurements for die attach characterization. We will also present a method for eliminating the very time consuming calibration process. Using the proposed methods even the in-line testing of LEDs can be accomplished.

Thermal management in System-on-Package structures by applying microscale heat sink. Part I

Since the first microchannel heat sink was introduced, intense research on microchannel based heat sinks has been conducted to study the heat transfer mechanism and fluid flow characteristics in microscale channel structures. In this paper the determination of proper channel length of the microscale heat sink(s) is presented. The main aim is to introduce a methodology to define the maximum applicable channel length in order to achieve the maximum heat transfer from the substrate to the fluid without realizing unnecessarily long channels. It is important because superfluous parts of the channel(s) from the heat transfer point of view occupy important areas where further channel(s) can be realized. The proposed characteristic channel length depends on the fluid properties, the flow rate and the channel geometries. This approach could be more important in the case of the more-than-Moore 3D integration (e.g.: System-in-Packages, stacked dies structure, etc.) where removing the heat from the inner layers or forming homogenous temperature distribution within a selected die is the most up-to-date question nowadays. The determination of the proper length of the channel(s) gives a basis to design the optimal architecture of microscale heat sink structures. The commonly applied microscale cooling structures with radial arrangement and one inlet usually reach the highest achievable heat transfer at low pressure drop but occupy more surface area than needed at applied flow rates.

Design of a static TIM tester

Nowadays the quality of thermal interface materials (TIM) has a growing importance as the increasing dissipation level of ICs requires more and more sophisticated solutions to reduce the Rth along the heat-flow path. The recent approach of TIM manufacturers is to use nanoparticles as fillings in TIM materials, in order to enhance considerably the TIM thermal conductivity. On the other hand this solution raises difficulties in the characterization of these materials. Namely, the resolution of the conventional methods is not high enough to measure resistance values as low as 0.01-0.05 Kcm2/W. This is the reason why we developed static TIM tester equipment using some new concepts. The main idea behind our design is to use the capabilities of microelectronics in order to make small sized sensors both for temperature and heat flux sensing. This way it is possible to place these sensors in the closest proximity of the measured sample. The status of this work is presented in the paper.

Thermal transient characterization of semiconductor devices with multiple heat sources-Fundamentals for a new thermal standard

The thermal performance of semiconductor devices is most often specified according to JEDEC standards JESD51 1-14 which describe precisely how various steady-state thermal metrics are to be measured. Most of these metrics represent a thermal resistance between the junction of a semiconductor and some reference; e.g. Rth-JA (Junction-to-ambient), Rth-JB (Junction-to-board), or Rth-JC (Junction-to-case). However all of the above thermal metrics characterize the steady-state behaviour and have been designed for semiconductors with a single heat source only. While the extension of a stationary thermal resistance Rth-JX to the corresponding transient thermal impedance Zth-JX is straightforward the adaptation of existing standards for the characterization of devices with multiple heat sources is far less obvious. This publication gives an overview on the theoretical framework which allows extending the existing thermal metrics in a compliant way.

Thermal characterization of multichip structures

The advances in electronic packaging made it possible to encapsulate several independent semiconductor dice into a single package. In the last decade many packaging configurations are realized which range from the multichip modules to the 3D stack-die structures. Thermal aware design of such structures become complex, though. To understand the thermal behavior of multichip structure containing multiple dissipating elements placed on different dice, the couplings between individual dice have to be characterized. To determine their thermal transfer impedance matrix (TTIM) is a practical way to describe the thermal relations. In this paper we demonstrate the method utilized for TTIM measurements and also show how thermal surroundings (e.g. the PCB the chip is mounted on) affect the thermal relations inside the package. In addition, the temperature dependent non-linearity of the TTIMs is also described.

Design of a Static TIM Tester

Testing the thermal properties of thermal interface material (TIM) has been a big challenge for decades. Recent development trends made this challenge even bigger, as now the values that have to be measured are extremely small. In this paper, we present a newly developed TIM tester equipment that is targeting to overcome all the problems that present industrial TIM testing methods face. The main idea behind our design is to use the capabilities of microelectronics in order to make small sized sensors both for temperature and heat-flux sensings. This way it is possible to place these sensors in the closest proximity of the measured sample. This paper presents details of all the technical solutions of the newly developed static TIM tester that is capable to measure R th of unit area values in the order of 0.01 K cm 2 / W with good accuracy. Special attention is made to analyze and eliminate the possible sources of measurement inaccuracy. A number of measurement examples prove the usability of the developed measuring instrument.

Enhanced thermal characterization method of microscale heatsink structures

In the frame of thermal management of electronic devices, finding efficient cooling solutions of the next generation equipment is a hot topic. If a new or improved solution is presented it always requires efficient characterization methods to prove the benefits compared to its predecessor. In case of microscale heatsink structures which are integral parts of modern chip or package level cooling concepts, an efficient measurement method is needed to analyse the performance of structures with different layouts and/or manufacturing technologies. This paper presents an enhanced thermal characterization method of microchannel based cooling structures, determining relevant partial thermal resistances from structure functions obtained by thermal transient testing. Our prior microscale heatsink characterization method was recently improved, accounting e.g. for possible nonlinearities of the heat transfer processes. This paper presents how we have improved our measurements setup in detail to deal with these phenomena compared to the previous setup.