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Dive into the research topics where Peter Gillingham is active.

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Featured researches published by Peter Gillingham.


IEEE Journal of Solid-state Circuits | 1991

High-speed, high-reliability circuit design for megabit DRAM

Peter Gillingham; Richard C. Foss; Valerie L. Lines; Gregg Shimokura; Tomasz Wojcicki

Circuit techniques for improving the speed and reliability of submicrometer geometry CMOS DRAMs are described. Double-bootstrap voltages are eliminated with an internal voltage supply and a unique word-line driver, reducing stress on short-channel devices. A row and column redundancy technique equivalent to physical disconnect of word lines and bit lines solves leakage problems. Speed enhancements are achieved through bit-line isolation for accelerated column access, a high-speed SRAM-style data path, and by tailoring sensing currents within the limitations of package inductance. The design of a fast 1-Mb DRAM employing these circuits is outlined. >


IEEE Journal of Solid-state Circuits | 1986

A 160-kb/s digital subscriber loop transceiver with memory compensation echo canceller

Roger Colbeck; Peter Gillingham

A full-duplex transceiver chip incorporating an adaptive echo canceling modem and a 2.048-Mb/s serial interface is described. The device provides a full-duplex communication link at 160 or 80 kb/s on up to 4 or 5 km, respectively, of 0.5-mm twisted-pair cable. Full integration is achieved through the use of RAM-based sign-algorithm echo-cancellation, biphase line code, a fixed switched-capacitor equalizer, and a digital phase locked loop. The authors emphasize system design considerations and a chip architecture minimizing power dissipation, silicon area, and off-chip components. A double poly 3-/spl mu/m CMOS technology is used to implement the 5-V 22-pin device which dissipates less than 50 mW and occupies 27.7 mm/SUP 2/.


Archive | 2003

Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory

Richard C. Foss; Peter Gillingham; Graham Allan


Archive | 2000

High voltage boosted word line supply charge pump and regulator for dram

Richard C. Foss; Peter Gillingham; Robert Harland; Valerie L. Lines


Archive | 2008

Clock mode determination in a memory system

Peter Gillingham; Graham Allan


Archive | 2000

Dynamic content addressable memory cell

Valerie Lines; Peter Gillingham; Abdullah Ahmed; Tomasz Wojcicki


Archive | 2006

Synchronous memory read data capture

Peter Gillingham; Robert Mckenzie


Archive | 2001

Matchline sense circuit and method

Stanley Jeh-Chun Ma; Peter P Ma; Valerie Lines; Peter Gillingham; Robert Mckenzie; Abdullah Ahmed


Archive | 2002

Boosted voltage supply

Richard C. Foss; Peter Gillingham; Robert Harland; Valerie L. Lines


Archive | 1993

Dynamic random access memory using imperfect isolating transistors

Richard C. Foss; Peter Gillingham; Robert Harland; Masami Mitsuhashi; Atsushi Wada

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