Peter M. Kelly

A programmable facilitating synapse device

We present a programmable dynamic charge transfer synapse (CTS) in a single semiconductor device. The CTS comprises a metal oxide semiconductor (MOS) transistor operating in subthreshold and two MOS capacitors in proximity to the transistor. One of the capacitors is permanently biased in strong inversion where the associated density of charge in the well implements the weighting. When a presynaptic spike is applied to the gate of the second MOS capacitor the charge density in the well falls producing a current spike at the output. The amplitude of the spike is correlated with the equilibrium charge density in the well, which is controlled by the associated gate voltage. Aggregation of spikes from an array of CTSs is achieved by using a current mirror configuration whose output postsynaptic potential can be used to stimulate a point neuron circuit. The function of the MOS transistor is to restore the charge in the well where the duration of this process is dictated by the associated gate voltage. Therefore, the synapse is capability of operating in the facilitating state over a large frequency range. The CTS is compact and since it operates in transient mode, its power consumption is negligible. Simulation results are presented which clearly demonstrate its operation.

Investigation of a programmable threshold logic gate array

A study of simulated InP-based RTD/HFET threshold logic gates (TLGs), deployed in an array suited to the implementation of programmable neural network-like architectures, is carried out. A new programmable TLG and an EX-OR TLG are presented. An array of programmable and non-programmable TLGs is studied to demonstrate an application with field programmability and to determine the suitability of the technology for the realisation of these gates in larger scale integrated circuits. The architecture may have the potential for a flexible platform that will allow training and reconfiguration of a cellular artificial neural network (ANN). The functionality of the circuit architecture is investigated and the effects of variations in device-characteristics, and clocked power supply on its operation are considered to assess the potential use of TLG circuits in the context of larger scale implementations.

On the Design of a Low Power Compact Spiking Neuron Cell Based on Charge-Coupled Synapses

A charge-coupled silicon synapse with a floating diffusion output is proposed as the basis for a new electronic, spiking neuron cell. The synapse is formed by a two-stage charge transfer device with the weight function stored in a floating gate over the first stage. The output of the synapses feeds into the multi-gate inputs of a MOSFET which themselves capacitively couple onto a common floating gate. This MOSFET provides a summing action and so acts as a point neuron. Thermal generation within the synaptic device, causes relaxation of the signals and this can be tailored to provide realistic postsynaptic potential (PSP) dependencies. Simulation results show that this architecture can generate a PSP that effectively mimics the spiking behaviour of real synapses. The cell is highly compact and intrinsically low power and so offers the potential for biologically plausible spiking neural networks (SNNs) in hardware.

On brain-inspired connectivity and hybrid network topologies

This paper starts from very fresh analyses comparing brainpsilas connectivity with those of well-known network topologies, based on the latest interpretation of Rentpsilas rule. Those analyses have revealed how close the brain comes to the latest Rentpsilas rule averages. On the other hand, all the known network topologies seems to fall short of being strong contenders for mimicking the brain. That is why this paper performs a detailed Rent-based (top-down) connectivity analysis of many two-level hybrid network topologies. This analysis aims to identify those two-level hybrid network topologies which are able to closely mimic brainpsilas connectivity. The ranges of granularity (as given by the total number of gates and the number of processors) where this mimicking is happening are identified. These results should have implications for the design of networks(-on-chip) and for the burgeoning field of multi/many-core processors (in the short to medium term), as well as for investigations on future nano-architectures (in the long run). Complementary results using a bottom-up approach have also been obtained, and will be mentioned.

A silicon synapse based on a charge transfer device for spiking neural network application

We propose a silicon synapse for spiking neural network application. In this endeavor, two major issues are addressed: the structure of the synapse and the associated behavior. This synaptic structure is basically a charge transfer device comprising of two Metal-Oxide-Semiconductor (MOS) capacitors the first of which stores the weight and the second controls its reading. In this work, simulation results prove that the proposed synapse captures the intrinsic dynamics of the biological synapse and exhibits a spike characteristic. The device operates at very low power and offers the potential for scaling to massively parallel third generation hardware neural networks.

On two-layer brain-inspired hierarchical topologies – a rent's rule approach –

This research compares the brains connectivity (based on different analyses of neurological data) with well-known network topologies (originally used in super-computers) using Rents rule. The comparison reveals that brain connectivity is in good agreement with Rents rule. However, the known network topologies fall short of being strong contenders for mimicking brains connectivity. That is why we perform a detailed Rent-based (top-down) connectivity analysis of generic two-layer hierarchical network topologies. This analysis aims to identify generic two-layer hierarchical network topologies which could closely mimic brains connectivity. The range of granularities (i.e., number of gates/cores/neurons) where such mimicking is possible are identified and discussed. These results should have implications for the design of future networks-on-chip in general, and for the burgeoning field of multi/many-core processors in particular (in the medium term), as well as for forward-looking investigations on emerging brain-inspired nano-architectures (in the long run).

Evaluating the training dynamics of a CMOS based synapse

Recent work by the authors proposed compact low power synapses in hardware, based on the charge-coupling principle, that can be configured to yield a static or dynamic response. The focus of this work is to investigate the training dynamics of these synapses. Empirical models of the Post Synaptic Response (PSP), derived from hardware simulations, were developed and subsequently embedded into the MATLAB environment. A network of these synapses was then used to solve a benchmark problem using a well established training algorithm where the performance metric was convergence time, accuracy and weight range; the Spike Response Model (SRM) was used to implement point neurons. Results are presented and compared with standard synaptic responses.

A Biologically Plausible Neuron Circuit

A neuron circuit is presented which can mimic the operation of a spiking neuron cell. A current mirror configuration allows the temporal summing of synaptic inputs, which are subsequently stored as a charge packet on the gate of a CMOS inverter: the inverter is coupled to a second inverter and feedback is used to facilitate re-setting the cell after firing. Charge leakage from the gate of the inverter, via a reverse biased p-n junction, provides a membrane decay time constant comparable with what is observed in biological neurons. Breadboard experiments and simulation results are presented to demonstrate the functionality of the neuron circuit.

A time multiplexing architecture for inter-neuron communications

This paper presents a hardware implementation of a Time Multiplexing Architecture (TMA) that can interconnect arrays of neurons in an Artificial Neural Network (ANN) using a single metal wire. The approach exploits the relative slow operational speed of the biological system by using fast digital hardware to sequentially sample neurons in a layer and transmit the associated spikes to neurons in other layers. The motivation for this work is to develop minimal area inter-neuron communication hardware. An estimate of the density of on-chip neurons afforded by this approach is presented. The paper verifies the operation of the TMA and investigates pulse transmission errors as a function of the sampling rate. Simulations using the Xilinx System Generator (XSG) package demonstrate that the effect of these errors on the performance of an SNN, pre-trained to solve the XOR problem, is negligible if the sampling frequency is sufficiently high.

Reducing interconnection resource overhead in nano-scale FPGAs through MVL signal systems

In nano-architectures, transistor counts place extreme demands on interconnection resources. The chronic problem of interconnect area versus device area becomes more acute than it currently is. Even with multilayering of conductors there may still be attenuation and propagation delay issues which at the extremes of nano-architecture severely limit performance. When reconfigurable devices such as field programmable gate arrays (FPGAs) are considered the issue of interconnection resources becomes even more acute due to the inherent redundancy already apparent in existing devices. The authors propose the use of a multiple valued signal system to increase functional density whilst reducing the interconnection resource overhead in FPGA based nano-architectures.