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Dive into the research topics where Peter Pessl is active.

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Featured researches published by Peter Pessl.


IEEE Journal of Solid-state Circuits | 2003

A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-/spl mu/m CMOS

Richard Gaggl; Andreas Wiesbauer; Gerhard Fritz; Christian Schranz; Peter Pessl

A high-resolution multibit sigma-delta analog-to-digital converter (ADC) implemented in a 0.18-/spl mu/m CMOS technology is introduced. The circuit is targeted for an asymmetrical digital subscriber line (ADSL) central-office (CO) application . An area- and power-efficient realization of a second-order single-loop 3-bit modulator with an oversampling ratio of 96 is presented. The /spl Sigma//spl Delta/ modulator features an 85-dB dynamic range over a 300-kHz signal bandwidth. The measured power consumption of the ADC core is only 15 mW. An innovative biasing circuitry is introduced for the switched-capacitor integrators.


european solid-state circuits conference | 2004

Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13/spl mu/m CMOS

D. Giotta; Peter Pessl; Martin Clara; W. Klatzer; Richard Gaggl

This work presents a 6-bit fully-differential current steering digital-to-analog converter (DAC), oversampled and 2/sup nd/ order noiseshaped. It is implemented in a 0.13 /spl mu/m standard CMOS process, using only regular threshold voltage devices. The circuit is targeted at ADSL2+ central-office (CO) applications. Clocked at 105 MHz from a low-jitter PLL, it yields a multi-tone power ratio (MTPR) higher than 75 dBc for DMT signals, with an output swing of 1.4 V peak-to-peak. It has an effective resolution of more than 14.5 ENOBs (effective number of bits), consuming only 9 mW from a single 1.5 V supply.


international solid-state circuits conference | 2004

A four-channel ADSL2+ analog front-end for CO applications with 75 mW per channel, built in 0.13-/spl mu/m CMOS

Peter Pessl; J. Hohl; Richard Gaggl; A. Marak; G. Glanzer; A. Kahl; S. Walter; J. Hauptmann

This paper describes a four-channel ADSL2+ analog front-end (AFE) targeted at a central office application, with a power consumption of 75 mW per channel. The design is implemented using a modern 0.13-/spl mu/m CMOS process. The AFE consists of a 14-bit ADC and DAC, a very low-noise high-linearity automatic gain control (AGC), analog filter blocks, and digital decimation and interpolation filter stages. The design has been optimized to achieve the lowest possible power consumption, high performance, and cost efficiency.


Archive | 2004

Tuning circuit for a filter

Richard Gaggl; Manfred Nopp; Peter Pessl; Christian Schranz; Dietmar Sträussnigg


Archive | 2001

Programmable echo cancellation filter

Antonio Digiandomenico; Peter Pessl; Christian Fleischhacker


Archive | 1999

CIRCUIT CONFIGURATION FOR QUANTISATION OF DIGITAL SIGNALS AND FOR FILTERING QUANTISATION NOISE

Jörg Hauptmann; Peter Pessl; Dietmar Sträussnigg


Archive | 2000

Line termination device for a telephone subscriber line

Joerg Hauptmann; Christian Schranz; Bernhard Zojer; Peter Pessl; David Schwingshackl; Herbert Zoler


Archive | 2005

Method and device for amplifying a reception signal

Alexander Kahl; Peter Pessl; Sergio Walter


Archive | 2001

Device and method for checking whether a signal with a predetermined frequency is being received

Alessandro Fulli; Peter Pessl; Christian Schranz; Michael Staber


Archive | 2006

Method for producing a protective assembly for protecting an electronic component from electrostatic discharge, and correspondingly configured electronic component

Peter Pessl

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