Richard Gaggl

A power optimized 14-bit SC /spl Delta//spl Sigma/ modulator for ADSL CO applications

A switched-capacitor multi-bit /spl Delta//spl Sigma/ ADC including a reference-voltage buffer is implemented in 0.13 /spl mu/m CMOS. The single loop 3 b modulator features 14 b and 13 b dynamic range over 276 kHz and 1.1 MHz signal bandwidths, respectively. Clocked at 105 MHz, the ADC core consumes 8 mW from a 1.5 V supply.

Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13/spl mu/m CMOS

This work presents a 6-bit fully-differential current steering digital-to-analog converter (DAC), oversampled and 2/sup nd/ order noiseshaped. It is implemented in a 0.13 /spl mu/m standard CMOS process, using only regular threshold voltage devices. The circuit is targeted at ADSL2+ central-office (CO) applications. Clocked at 105 MHz from a low-jitter PLL, it yields a multi-tone power ratio (MTPR) higher than 75 dBc for DMT signals, with an output swing of 1.4 V peak-to-peak. It has an effective resolution of more than 14.5 ENOBs (effective number of bits), consuming only 9 mW from a single 1.5 V supply.

An energy-efficient 17-bit noise-shaping Dual-Slope Capacitance-to-Digital Converter for MEMS sensors

A noise-shaping Dual-Slope (DS) Capacitance-to-Digital Converter (CDC), specifically designed for interfacing capacitive MEMS sensors, is presented. In particular, this work proposes a design with a MEMS sensor built with a bridge of capacitors. In this bridge, some capacitors are function of the pressure in order to obtain a variation in the output of the bridge related with the change of pressure. Then, the capacitive to digital conversion is realized using two steps. First, a Switched-Capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a time domain noise-shaping Dual-Slope ADC is used to digitalize the magnitude of the capacitive bridge. The use of time instead of amplitude resolution leads to the following strengths: 1) intrinsically small sensitivity to temperature and process variations; 2) simplicity of trimming offset and gain to correct the sensor parameter spread; and 3) area and energy efficient implementation. The effectiveness of the method is demonstrated by measurements performed on a prototype, designed and fabricated using standard digital 0.13μm CMOS technology. Experimental results show that it achieves a resolution of 17-bit, which corresponds to a capacitive resolution of 5.4aF, while consuming only 146μA from a 1.5V power supply, with an effective area of 0.317mm2.

A 65-nm 84-dB-gain 200-MHz-UGB CMOS fully-differential three-stage amplifier with a novel Common Mode control

A single miller capacitor feedforward compensation (SMFFC) technique with a novel common mode (CM) control circuitry for fully-differential multistage amplifiers is presented in this paper. The novel alternative to control the output common-mode voltage, adding a feed-forward path to a normal common-mode feed-back (CMFB) amplifier, allows to have a very stable and wide-band regulation. A fully-differential three-stage amplifier based on this approach has been implemented in 65-nm CMOS technology. A DC-gain of 84-dB and a bandwidth of 200-MHz are achieved, driving a 25-kOmega//1-pF load. Thanks to the novel control circuitry, the CM path achieved 136-MHz bandwidth with 85-dB DC-gain. The power consumption is 10.17-mW with a 1-V power supply. It occupies 0.02-mm2 of silicon area.

A High-Resolution Self-Oscillating Integrating Dual-Slope CDC for MEMS Sensors

An integrating dual-slope (DS) capacitance-to-digital converter (CDC), specifically designed for interfacing capacitive MEMS sensors, is presented. In particular, this work proposes a CDC that interfaces a MEMS sensor built with a bridge of capacitors. In this bridge, some capacitances are pressure sensitive, causing pressure-related changes in the bridge output. The voltage to digital conversion is then realized in two steps. First, a voltage amplifier boosts the output of the bridge. Second, an integrating DS ADC digitizes the output of the amplifier. The proposed ADC uses time instead of amplitude resolution to generate a multi-bit digital output stream. In addition, it performs noise shaping of the quantization error to reduce measurement time. These characteristics lead to the following properties: intrinsically low sensitivity to temperature and process variations, simplicity of trimming offset and gain to correct for sensor parameter spread, and an energy-efficient implementation. The effectiveness of the proposed architecture is demonstrated by measurements performed on a prototype, designed, and fabricated using standard 0.13 μm CMOS technology. Experimental results show that the proposed CDC achieves a maximum resolution of 17 bits, which corresponds to a capacitive resolution of 5.4aF, while consuming only 146 μA from a 1.5 V power supply, with an effective area of 0.317mm2.

A MOX gas sensors resistance-to-digital CMOS interface with 8-bits resolution and 128dB dynamic range for low-power consumer applications

In this paper an interface circuit for MOX gas sensor is presented. It is based on a resistance-to-frequency converter and improves existing solutions in term of performance (offset) and power efficiency. The resistive range covered is 100Ω-1MΩ, with an equivalent 8-bit precision in a total measurement time of 1 second. This corresponds to a dynamic range of about 128dB. Power consumption and design strategy are optimized for mass production targeting consumer applications. The interface is implemented in a standard CMOS 130nm technology with an area of 125000 μm2 and 450μA of current consumption.

A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator

Capacitive or resistive sensors can be included in the feedback network of an oscillator to implement a data acquisition system. A higher sampling rate, compared with standard oversampled converters, is required to maintain a sufficient SNR in this case. In this paper, we propose an architecture based on a LC-CMOS oscillator and a digital interface that can be completely integrated on chip and satisfies low clock specifications of standard microphone capacitive interfaces. The complete system outputs one-bit bitstream at 15.53MHz and achieves SNR of 55.38dB for -26dBfs input tone.

Limitations of Delta-Sigma Converters

This chapter gives an brief overview of A/D-conversion focusing on delta-sigma modulators. For a comprehensive analysis of delta-sigma converters the reader is referred to later mentioned references. The sampling and quantization of analog signals is briefly discussed. The main converter specification items are introduced. Next, the principle of oversampling and delta-sigma conversion is covered followed by some architectural aspects and implementation approaches. Pulse-width modulation will be introduced based on a delta-sigma modulator for low voltage applications. Finally, the impact on jitter for A/D-conversion is briefly discussed.

9.5 A 1.8V true-differential 140dB SPL full-scale standard CMOS MEMS digital microphone exhibiting 67dB SNR

Over the last few years, robust MEMS microphones have gained significant market share in consumer applications such as mobile phones and hearing aids. The consumer market is demanding improved quality for audio recording, while also being capable of suppressing high-energy disturbers, e.g., wind noise. The challenge is to achieve both high DR and SNR at low supply voltages that limit signal swing. Signal levels are expressed in dB Sound-Pressure-Level (dB SPL) with respect to the human hearing threshold at a sound pressure of 20µPa corresponding to 0dB SPL. Todays mass-market MEMS digital microphone solutions typically process sound up to 120dB SPL [1,2].

A novel architecture for a Capacitive-to-Digital Converter using time-encoding and noise shaping

This paper presents a Capacitive-to-Digital Converter (CDC) for MEMS sensors using a time-encoding approach. A common CDC needs an intermediate Capacitive-to-Voltage (CV) stage to perform such a conversion. Instead, this architecture directly transforms the sensor capacitor quantity to a digital value. Additionally it is intended to give flexibility at reduced chip area. The proposed solution maps amplitude information into time domain using an integrating Dual-Slope (DS) converter. Furthermore, this CDC employs quantization error noise shaping to reduce measurement time. Both techniques, namely scaling of the CDC resolution and power consumption, will lead to an efficient implementation without extra cost in area. Auto-zeroing further suppresses the offset and low frequency noise of the amplifier. Simulation results show that a realization in digital CMOS technology will be a promising candidate for a scalable CDC for MEMS sensors.