Peter S. Magnusson

Simics: A full system simulation platform

Full system simulation seeks to strike a balance between accuracy and performance. Many of its possibilities have been obvious to practitioners in both academia and industry for quite some time, perhaps decades, but Simics supports more of these possibilities within a single framework than other tools do. Simics is a platform for full system simulation that can run actual firmware and completely unmodified kernel and driver code. It is sufficiently abstract to achieve tolerable performance levels, and it provides both functional accuracy for running commercial workloads and sufficient timing accuracy to interface to detailed hardware models. Simics can also run a heterogeneous network of systems from different vendors within the same framework. Exceptionally fast, Simics can easily add new components and leverage older ones within a practical abstraction level. It offers a platform with a rich API and a powerful scripting environment for use in a broad range of applications.

Queue locks on cache coherent multiprocessors

Large-scale shared-memory multiprocessors typically have long latencies for remote data accesses. A key issue for execution performance of many common applications is the synchronization cost. The communication scalability of synchronization has been improved by the introduction of queue-based spin-locks instead of Test&(Test&Set). For architectures with long access latencies for global data, attention should also be paid to the number of global accesses that are involved in synchronization. We present a method to characterize the performance of proposed queue lock algorithms, and apply it to previously published algorithms. We also present two new queue locks, the LH lock and the M lock. We compare the locks in terms of performance, memory requirements, code size and required hardware support. The LH lock is the simplest of all the locks, yet requires only an atomic swap operation. The M lock is superior in terms of global accesses needed to perform synchronization and still competitive in all other criteria. We conclude that the M lock is the best overall queue lock for the class of architectures studied.<<ETX>>

Efficient memory simulation in SimICS

We describe novel techniques used for efficient simulation of memory in SimICS; an instruction level simulator developed at SICS. The design has focused on efficiently supporting the simulation of multiprocessors, analyzing complex memory hierarchies and running large binaries with a mixture of system level and user level code. A software caching mechanism (the Simulator Translation Cache, STC) improves the performance of interpreted memory operations by reducing the number of calls to complex memory simulation code. Major data structures are allocated lazily to reduce the size of the simulator process. A well defined internal interface to generic memory simulation simplifies user extensions. Leveraging on a flexible interpreter based on threaded code allows runtime selection of statistics gathering, memory profiling, and cache simulation with low overhead. The result is a memory simulation scheme that supports a range of features for use in computer architecture research, program profiling, and debugging.<<ETX>>

Using complete system simulation for temporal debugging of general purpose operating systems and workloads

Digital convergence is precipitating the addition of soft real-time applications to mainstream desktop and server operating environments. Most traditional debuggers for mainstream systems lack a notion of temporal correctness, making them unsuitable for real-time system design and analysis. We propose leveraging complete system simulation to build a temporal debugger which is capable of analyzing mixed real-world workloads. Traditional real-time system debuggers based on simulation utilize slow, but accurate, simulators. Complete system simulators accept an approximate model of time in exchange for higher performance. The higher performance allows these simulators to analyze high-end commercial operating systems and applications. We describe a temporal debugger design based on complete system simulation and report on some early experiences in analyzing a simple workload. The tool offers a non-intrusive, predictable environment for debugging complex workloads with partial real-time constraints. The simulator foundation allows for interactive debugging of time-critical sequences while preserving a model of execution time flow.

Efficient instruction cache simulation and execution profiling with a threaded-code interpreter

We describe novel techniques used for efficient simulation of memory in SimICS, an instruction level simulator developed at SICS. The design has focused on efficiently supporting the simulation of multiprocessors, analyzing complex memory hierarchies and running large binaries with a mixture of system-level and user-level code. A software caching mechanism (the Simulator Translation Cache, STC) improves the performance of interpreted memory operaions by reducing the number of calls to complex memory simulation code. A lazy memory allocation scheme reduces the size of the simulator process. A well-defined internal interface to generic memory simulation simplifies user extensions. Leveraging on a flexible interpreter based on threaded code allows runtime selection of statistics gathering, memory profiling, and cache simulation with low overhead. The result is a memory simulation that supports a range of features for use in computer architecture research, program profiling, and debugging.

The virtual test lab

Systems companies today face increasingly complex and expensive testing challenges that require innovative solutions. One approach to address the problem uses full-system simulation with virtual hardware early on and throughout the development process. Recent technological advances in virtualization now satisfy the demands of software development, enabling the construction of a software model of the complete system that can run on the developers desktop PC. Virtualization is so accurate it can run the fabled golden code - the actual binary that ships in the final product. A virtual test laboratory can simulate not only the system being tested but also the other systems it interacts with.

A hybrid simulation approach enabling performance characterization of large software systems

We describe a method for performance analysis of large software systems that combines a fast instruction-set simulator with off-line detailed analysis of segments of the execution. The combination is faster than straight cycle-accurate simulation, simpler and more flexible than techniques relying on hardware monitoring, and accurate. Specifically, the instruction-set simulator running at a slowdown of around 50, maintains enough target state throughout the execution that an arbitrarily collected segment of the instruction trace is sufficient input for a post-processing, cycle-accurate model of the processor and memory hierarchy. We present a case study to support our contention that a reduced state is sufficient as input to a cycle-accurate simulator. We use a commercial M88110-based prototype system as a reference point, and show that for three trace segments, the cycle-accurate post-processing gives reliable data to do system optimization.