Peter Stubberud

A 2-GHz analog-to-digital delta-sigma modulator for CDMA receivers with 79-dB signal-to-noise ratio in 1.23-MHz bandwidth

This paper presents the design of a second-order single-bit analog-to-digital continuous-time delta-sigma modulator (CT-/spl Delta//spl Sigma/M) that can be used in wireless CDMA receivers. The CT-/spl Delta//spl Sigma/M samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79-dB signal-to-noise ratio (SNR) over a 1.23-MHz bandwidth. The CT-/spl Delta//spl Sigma/M was fabricated in a 0.18-/spl mu/m 1-poly 6-metal, CMOS technology and has an active area of approximately 0.892 mm/sup 2/. The /spl Delta//spl Sigma/Ms critical performance specifications are derived from the CDMA receiver specifications.

Adaptive image restoration of text images that contain touching or broken characters

To improve the performance of an optical character recognition (OCR) system, an adaptive technique that restores touching or broken character images is proposed. By using the output from an OCR system and a distorted text image, this technique trains an adaptive restoration filter and then applies the filter to the distorted text image that the OCR system could not recognize. To demonstrate the performance of this technique, two synthesized images containing only touching characters and two synthesized images containing only broken characters were processed. The results show that this technique can improve both pixel and character accuracy of text images containing touching or broken characters.

The design of frequency sampling filters by the method of Lagrange multipliers

A technique is developed for designing linear phase frequency sampling filters where the interpolation errors between frequency samples are controlled by minimizing the mean square error between the desired and actual frequency responses in the stopband subject to constraints on the passband frequency response. The frequency sampling filter design problem is defined as a constrained optimization problem, which is solved using the Lagrange multiplier optimization method. The Lagrange multiplier optimization method results in a set of linear equations, the solution of which determines the filters coefficients. >

A frequency sampling filter design method which accounts for finite word length effects

System functions of frequency sampling filters require pole-zero cancellations on the unit circle. For practical implementations, finite word length effects usually prevent pole-zero cancellations which can result in filter instability. The article develops an optimization method for designing a modified frequency sampling filter which is guaranteed to be stable. >

An analysis of dynamic element matching flash digital-to-analog converters

Although many dynamic element matching (DEM) digital-to-analog converters (DACs) have identical architectures, analyses of DEM DACs have been specific to the DAC DEM algorithm or based on simulation results. In this paper, a commonly used flash DEM DAC architecture is analyzed. Using this analysis, a DEM DACs mean integral nonlinearity (INL), variance of the LNL, output signal-to-distortion ratio, output signal-to-(noise plus distortion) ratio, and spurious-free dynamic range can be calculated theoretically. These theoretical measures can be used as criteria for comparing the performance of different DEM algorithms applied to the particular flash DEM DAC architecture analyzed in this paper. As an example, two new DEM algorithms-a barrel shift network controlled by a white stochastic signal and a generalized cube interconnection network (GCN) controlled by a colored stochastic signal-are introduced and compared with two stochastic DEM algorithms: a Benes network and a GCN-both of which are controlled by a white stochastic signal-and one deterministic DEM algorithm called clock-level averaging. In the example, the performance criteria are calculated theoretically and by simulation.

An analysis of flash dynamic element matching analog to digital converters

In this paper, a flash dynamic element matching (DEM) analog to digital converter (ADC) architecture is analyzed, and criteria are developed for comparing this architectures performance when various DEM algorithms are applied to it. As an example, these performance criteria are used to compare four DEM algorithms applied to a 6 bit flash DEM ADC.

CMOS current mode flash analog to digital converter

A high speed CMOS current mode flash analog to digital converter is proposed. The design uses a generic cell structure that decreases circuit area for large implementations of the design. A single cell is tested for design constraints, and design constraint solutions are discussed.

A comparison of hardware efficient dynamic element matching networks for digital to analog converters

Many dynamic element matching (DEM) algorithms for digital to analog use interconnection networks. In this paper, performance metrics that can compare interconnection networks used in DEM algorithms are introduced. Using these performance metrics, several interconnection networks are compared. Finally, two new hardware efficient networks for DEM are introduced.

An analysis of dynamic element matching digital to analog converters

Although many dynamic element matching (DEM) digital to analog converters (DACs) have identical architectures, analyses of DEM DACs have been specific to the DACs DEM technique. In this paper, a particular DEM DAC architecture is analyzed and criteria are developed for comparing this architectures performance when various DEM techniques are applied to it.

Generalized cube networks for implementing dynamic element matching digital-to-analog converters

Dynamic element matching (DEM) has been used to increase the spurious free dynamic range of digital to analog converters (DACs). In this paper, two DEM networks, the Full Randomization DEM (FRDEM) network and the binary tree (BT) network, are shown to be equivalent to an appropriately connected generalized cube network (GCN). A comparison of these two networks and the GCN shows that the BT network has the lowest hardware complexity for two to six bit DACs and that the FRDEM network has the lowest hardware complexity for DACs with seven bits or more.