J.W. Bruce

Efficient adder circuits based on a conservative reversible logic gate

Conservative and reversible logic gates are widely known to be compatible with revolutionary computing paradigms such as optical and quantum computing. A fundamental conservative reversible logic gate is the Fredkin gate. This paper presents efficient adder circuits based on the Fredkin gate. Novel full adder circuits using Fredkin gates air proposed which have lower hardware complexity than the current state-of-the-art, while generating the additional signals required for carry skip adder architectures. The traditional ripple carry adder and several carry skip adder topologies are compared. Theoretical performance of each adder is determined and compared. Although the variable sized block carry skip adder is determined to have shorter delay than the fixed block size carry skip adder, the performance gains are not sufficient to warrant the required additional hardware complexity.

Cooperative and progressive design experience for embedded systems

This paper describes a cooperative experiential learning activity to develop embedded systems design skills. Student teams design, build, and troubleshoot a microcontroller-based project composed of common embedded systems peripherals, including input/output and electromechanical devices, industry standard communication networks, and complex digital integrated circuits. The design experience is progressive, requiring each successive subsystem to be incorporated without disturbing previously completed subsystems. Furthermore, the design experience is based on a problem-based learning approach that motivates student learning and develops skills required by the student in a future professional capacity. These skills include designing to specification, use of third-party intellectual property, teamwork, communication, and lifelong learning skills. The design experience was offered to a cohort in conjunction with lectures using active learning techniques. Course evaluations were obtained from students and external reviewers, and the results show that the course was well received and achieved its educational objectives.

Nyquist-rate digital-to-analog converter architectures

This article covers two popular types of Nyquist-rate digital-to-analog converters (DACs): the flash DAC and the serial DAC. Flash DACs perform their conversion in a single clock cycle and are typically designed to operate at high-speeds. Serial DACs convert the digital signal to an analog signal one bit at a time. Serial DACs trade the hardware complexity of a flash DAC for longer conversion times. In this article, three variations of flash DACs are introduced along with two serial DACs. Also the advantages and disadvantages for each architecture are discussed.

Personal digital assistant (PDA) based I2C bus analysis

Personal digital assistants are lightweight, inexpensive, and ubiquitous. Furthermore, they have desktop class operating systems features supported by industrial strength development tools. These devices provide an ideal platform for deploying a practical platform for I2C bus analysis. In this paper, we propose a low-cost, highly portable I2C bus analyzer on a PalmOS based PDA. We describe the hardware interface, the supporting libraries, and the PalmOS-complaint application. The proposed approach is flexible and supports the creation of additional bus analyzer applications by third parties. The example bus analyzer application described here provides three operating modes, passive snooping, active bus mastering, and active slave device emulation. Each mode function over number of user-selectable data rates.

An analysis of dynamic element matching flash digital-to-analog converters

Although many dynamic element matching (DEM) digital-to-analog converters (DACs) have identical architectures, analyses of DEM DACs have been specific to the DAC DEM algorithm or based on simulation results. In this paper, a commonly used flash DEM DAC architecture is analyzed. Using this analysis, a DEM DACs mean integral nonlinearity (INL), variance of the LNL, output signal-to-distortion ratio, output signal-to-(noise plus distortion) ratio, and spurious-free dynamic range can be calculated theoretically. These theoretical measures can be used as criteria for comparing the performance of different DEM algorithms applied to the particular flash DEM DAC architecture analyzed in this paper. As an example, two new DEM algorithms-a barrel shift network controlled by a white stochastic signal and a generalized cube interconnection network (GCN) controlled by a colored stochastic signal-are introduced and compared with two stochastic DEM algorithms: a Benes network and a GCN-both of which are controlled by a white stochastic signal-and one deterministic DEM algorithm called clock-level averaging. In the example, the performance criteria are calculated theoretically and by simulation.

CMOS current mode interpolating flash analog to digital converter

A high speed CMOS current-mode interpolating flash analog-to-digital converter capable is proposed. The design uses generic cells to generate all current comparator inputs. The proposed interpolation technique reduces the transistor count and power consumption of a pure flash implementation while improving SNR, SFDR, and DNL. Five-bit interpolating flash and pure flash designs were implemented in 0.5 mm CMOS to compare performance characteristics.

An analysis of flash dynamic element matching analog to digital converters

In this paper, a flash dynamic element matching (DEM) analog to digital converter (ADC) architecture is analyzed, and criteria are developed for comparing this architectures performance when various DEM algorithms are applied to it. As an example, these performance criteria are used to compare four DEM algorithms applied to a 6 bit flash DEM ADC.

CMOS current mode flash analog to digital converter

A high speed CMOS current mode flash analog to digital converter is proposed. The design uses a generic cell structure that decreases circuit area for large implementations of the design. A single cell is tested for design constraints, and design constraint solutions are discussed.

A comparison of hardware efficient dynamic element matching networks for digital to analog converters

Many dynamic element matching (DEM) algorithms for digital to analog use interconnection networks. In this paper, performance metrics that can compare interconnection networks used in DEM algorithms are introduced. Using these performance metrics, several interconnection networks are compared. Finally, two new hardware efficient networks for DEM are introduced.

Generalized cube networks for implementing dynamic element matching digital-to-analog converters

Dynamic element matching (DEM) has been used to increase the spurious free dynamic range of digital to analog converters (DACs). In this paper, two DEM networks, the Full Randomization DEM (FRDEM) network and the binary tree (BT) network, are shown to be equivalent to an appropriately connected generalized cube network (GCN). A comparison of these two networks and the GCN shows that the BT network has the lowest hardware complexity for two to six bit DACs and that the FRDEM network has the lowest hardware complexity for DACs with seven bits or more.