Petra Backus

Nickel-palladium bond pads for copper wire bonding

The semiconductor packaging industry is undergoing a step-change transition from gold to copper wire bonding brought on by a quadrupling of gold cost over the last 8 years. The transition has been exceptionally rapid over the last 3 years and virtually all companies in the industry now have significant copper wire bonding production. Among the challenges to copper wire bonding is the damage to bond pads that had been engineered for wire bonding with the softer gold wire. This paper presents an extensive evaluation of electroless NiPd and NiPdAu bond pads that offer a much more robust alternative to the standard Al pad finish. These NiPd(Au) bond are shown to outperform Al in virtually all respects: bond strength, bond parameter window, lack of pad damage and reliability.

Fabrication and characterization of fine pitch on-chip copper interconnects for advanced wafer level packaging by a high aspect ratio through AZ9260 resist electroplating

In this paper, we report the fabrication of high aspect ratio, highly dense, very fine pitch on-chip copper-pillar-based interconnects for advanced packaging applications. Photoresist molds up to a thickness of 80 µm and having feature sizes as small as 5 µm were fabricated using multi-step coating of the positive tone AZ9260 photoresist. Spin coating and lithography parameters were optimized to achieve smooth and vertical sidewalls. Copper interconnects having an aspect ratio up to 6 and a pitch size of 25 µm were electroplated in the fabricated resist mold. Due to a very small pitch size, the total number of interconnects per cm2 chip area is 160 000, which is much larger than the conventional solder-based interconnects. The electrical resistance of the electroplated copper interconnects was measured by 4-probe kelvin measurement configuration and was found to be in the range of 8–10 mΩ and the corresponding electrical resistivity was calculated as 2.4 µΩ cm. Such low resistive interconnects can carry much larger electrical current without significant electrical loss, which is ideally suitable for next generation packaging applications. X-ray diffraction has shown the presence of the (2 2 0) texture along the length of electroplated copper pillars. Transmission electron microscope reveals the presence of nanoscale copper twins along the length of copper interconnects.

Mechanical and microstructure characterization of high aspect ratio electroplated through-wafer copper interconnects

In this paper, we present the mechanical characterization of high aspect ratio through-wafer electroplated copper interconnects. Copper was deposited in very high aspect ratio (~15) and narrow DRIE etched through-vias (15 mum) in silicon substrate by a special electrodeposition technique. Since the basic understanding of the mechanical and material properties of electroplated copper is very critical for the development of next generation electronic devices and 3D wafer level packaging, these properties and the grain structure of electroplated copper were measured by appropriate characterization techniques. The elastic modulus and the hardness of electroplated copper were measured by nanoindentation continuous stiffness measurement, while the grain structure of electroplated copper was found out by atomic force microscope. The induced strain, a result of mismatch in coefficient of thermal expansion, was studied by digital image speckle correlation analysis, when the copper interconnects were subjected to a temperature cycle from 25degC to 125degC. The Youngs modulus and the hardness of electroplated copper interconnects measured at the top of interconnects (150 GPa and, 2.4 GPa, respectively) were found to be higher than the measured values at the cross-section of copper pillars (136 GPa and, 2.0 GPa respectively). It was found that the indentation modulus along the {111} plain is about 10-25% more than that along {100}. As a result of this difference, the copper pillars form texture and have preferred crystal orientation along the z-axis