Petri Kukkala

UML-based multiprocessor SoC design framework

This paper describes a complete design flow for multiprocessor systems-on-chips (SoCs) covering the design phases from system-level modeling to FPGA prototyping. The design of complex heterogeneous systems is enabled by raising the abstraction level and providing several system-level design automation tools. The system is modeled in a UML design environment following a new UML profile that specifies the practices for orthogonal application and architecture modeling. The design flow tools are governed in a single framework that combines the subtools into a seamless flow and visualizes the design process. Novel features also include an automated architecture exploration based on the system models in UML, as well as the automatic back and forward annotation of information in the design flow. The architecture exploration is based on the global optimization of systems that are composed of subsystems, which are then locally optimized for their particular purposes. As a result, the design flow produces an optimized component allocation, task mapping, and scheduling for the described application. In addition, it implements the entire system for FPGA prototyping board. As a case study, the design flow is utilized in the integration of state-of-the-art technology approaches, including a wireless terminal architecture, a network-on-chip, and multiprocessing utilizing RTOS in a SoC. In this study, a central part of a WLAN terminal is modeled, verified, optimized, and prototyped with the presented framework.

UML 2.0 Profile for Embedded System Design

The unified modeling language (UML) 2.0 is emerging in the area of embedded system design. This paper presents a new UML 2.0 profile - called TUT-profile - that introduces a set of stereotypes and design rules for an application, platform, and mapping. The profile classifies different application and platform components, and enables their parameterization. The TUT-profile concentrates on the structure of an application and platform, and utilizes standard UML 2.0 for the behavioral modeling. The application is seen as a set of active classes with an internal behavior. Correspondingly, the platform is seen as a component library with a parameterized presentation in UML 2.0 for each library component.

TUTWLAN --- QoS Supporting Wireless Network

Quality of Service (QoS) support has generally been lacking from WPAN and WLAN technologies, which has motivated the research of TUTWLAN. Design objectives have been relatively simple network architecture and capability to support real time services ranging from sensor data to multimedia streaming. The main TUTWLAN entities for QoS support are the Medium Access Control (MAC) protocol called TUTMAC and TUTWLAN Access Point (AP). The channel access is based on dynamic reservation Time Division Multiple Access (TDMA). TUTWLAN is shown to be suitable for wireless home and office applications. It provides flexibility, interoperability and availability of services exceeding the recent QoS proposals that has been accounted at the standardisation bodies for standard wireless technologies.

Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications

This paper presents the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0. The platform is comprised of multiple Altera Nios II softcore processors and custom hardware accelerators connected by the heterogeneous IP block interconnection (HIBI) communication architecture. Each processor has a local copy of eCos real-time operating system for the scheduling of multiple application threads. The mapping of a UML application into the proposed platform is presented by distributing a WLAN medium access control protocol onto multiple CPUs. The experiments performed on FPGA show that our approach raises system design to a new level. To our knowledge, this is the first real implementation combining a high-level design flow with a synthesizable platform

Performance Modeling and Reporting for the UML 2.0 Design of Embedded Systems

This paper presents a new performance modeling approach for the design of embedded real-time systems using UML 2.0. The approach responds to the lack of specific semantics for the performance modeling. The existing UML metamodel is extended by defining stereotypes to include the message latency and execution time in UML statecharts. The information may contain both the real-time constraints and measured values that are back-annotated to the UML model. Further, fully automated model transformation is used to visualize this information with sequence diagrams. The modeling approach has been prototyped with the UML implementation of a WLAN medium access control protocol. The experiences proved the approach to be practical and intuitive.

UML 2.0 implementation of an embedded WLAN protocol

This paper evaluates the suitability of the new Unified Modelling Language (UML) 2.0 for the design and implementation of embedded wireless local area network (WLAN) protocols. UML 2.0 introduces several new features and improvements to semantics, diagram types, and notations of the language. Behaviour in UML 2.0 can be described accurately and precisely, which enables automatic source code (C/C++ for example) generation for creating executable models. A medium access control (MAC) protocol called TUTMAC was designed and implemented with UML 2.0, and integrated into a hardware platform. The implementation with UML 2.0 reached adequate performance for the protocol with time-critical functionality on the target platform.

Automated distribution of UML 2.0 designed applications to a configurable multiprocessor platform

This paper presents automated distribution of embedded real-time applications modeled in Unified Modeling Language version 2.0 (UML 2.0). The automated distribution requires methods and tools for design automation, as well as the run-time environment for the distributed execution on the target platform. Executable application code is generated from UML models, and UML with a custom profile is used to abstract hardware architecture and configure application mapping. For experimenting, a full featured WLAN terminal was designed in UML and implemented as a distributed multiprocessor system-on-chip (SoC) on an FPGA prototype platform. Measurements show that a 50-70% reduction in protocol delays is achived with distribution, and delay variations are reduced 45-85%.

Dynamic power management for UML modeled applications on multiprocessor SoC

The paper presents a novel scheme of dynamic power management for UML modeled applications that are executed on a multiprocessor System-on-Chip (SoC) in a distributed manner. The UML models for both application and architecture are designed according to a well-defined UML profile for embedded system design, called TUT-Profile. Application processes are considered as elementary units of distributed execution, and their mapping on a multiprocessor SoC can be dynamically changed at run-time. Our approach on the dynamic power management balances utilized processor resources against current workload at runtime by (1) observing the processor and workload statistics, (2) re-evaluating the amount of required resources (i.e. the number of active processors), and (3) re-mapping the application processes to the minimum set of active processors. The inactive processors are set to a power-save state by using clock-gating. The approach integrates the well-known power management techniques tightly with the UML based design of embedded systems in a novel way. We evaluated the dynamic power management with a WLAN terminal implemented on a multiprocessor SoC on Altera Stratix II FPGA containing up to five Nios II processors and dedicated hardware accelerators. Measurements proved up to 21% savings in the power consumption of the whole FPGA board.

Implementing a WLAN video terminal using UML and fully automated design flow

This case study presents UML-based design and implementation of a wireless video terminal on a multiprocessor system-on-chip (SoC). The terminal comprises video encoder and WLAN communications subsystems. In this paper, we present the UML models used in designing the functionality of the subsystems as well as the architecture of the terminal hardware. We use the Koski design flow and tools for fully automated implementation of the terminal on FPGA. Measurements were performed to evaluate the performance of the FPGA implementation. Currently, fully software encoder achieves the frame rate of 3.0 fps with three 50 MHz processors, which is one half of a reference C implementation. Thus, using UML and design automation reduces the performance, but we argue that this is highly accepted as we gain significant improvement in design efficiency and flexibility. The experiments with the UML-based design flow proved its suitability and competence in designing complex embedded multimedia terminals.

Design and implementation of a WLAN terminal using UML 2.0 based design flow

This paper presents a UML 2.0 based design flow for real-time embedded systems. The flow starts with UML 2.0 application, architecture and mapping models for our TUTWLAN terminal with its medium access control protocol. As a result, the hardware/software implementation on Altera Excalibur FPGA is achieved. Implementation utilizes eCos real-time operating system, and hardware accelerators for time-critical protocol functions. The design flow is prototyped in practice showing rapid UML 2.0 application model modification, real-time protocol processing in an image transfer application, and execution monitoring.