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Dive into the research topics where Phanindra K. Mannava is active.

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Featured researches published by Phanindra K. Mannava.


formal methods in computer aided design | 2004

A Simple Method for Parameterized Verification of Cache Coherence Protocols

Ching-Tsun Chou; Phanindra K. Mannava; Seungjoon Park

We present a simple method for verifying the safety properties of cache coherence protocols with arbitrarily many nodes. Our presentation begins with two examples. The first example describes in intuitive terms how the German protocol with arbitrarily many nodes can be verified using a combination of Murphi model checking and apparently circular reasoning. The second example outlines a similar proof of the FLASH protocol. These are followed by a simple theory based on the classical notion of simulation proofs that justifies the apparently circular reasoning. We conclude the paper by discussing what remains to be done and by comparing our method with other approaches to the parameterized verification of cache coherence protocols, such as compositional model checking, machine-assisted theorem proving, predicate ion, invisible invariants, and cut-off theorems.


formal methods | 2003

Experience with Applying Formal Methods to Protocol Specification and System Architecture

Mani Azimi; Ching-Tsun Chou; Akhilesh Kumar; Victor W. Lee; Phanindra K. Mannava; Seungjoon Park

In the last three years or so we at Enterprise Platforms Group at Intel Corporation have been applying formal methods to various problems that arose during the process of defining platform architectures for Intels processor families. In this paper we give an overview of some of the problems we have worked on, the results we have obtained, and the lessons we have learned. The last topic is addressed mainly from the perspective of platform architects.


Archive | 2004

Dynamically modulating link width

Naveen Cherukuri; Aaron T. Spink; Phanindra K. Mannava; Tim Frodsham; Jeffrey R. Wilcox; Sanjay Dabral; David S. Dunning; Theodore Z. Schoenborn


Archive | 2007

Link power saving state

Naveen Cherukuri; Jeffrey R. Wilcox; Sanjay Dabral; Phanindra K. Mannava; Aaron T. Spink; David S. Dunning; Tim Frodsham; Theodore Z. Schoenborn


Archive | 2001

Link level retry scheme

Ching-Tsun Chou; Suresh Chittor; Andalib Khan; Akhilesh Kumar; Phanindra K. Mannava; Rajee S. Ram; Sujoy Sen; Srinand Venkatesan; Kiran A. Padwekar


Archive | 2006

Avoiding deadlocks in a multiprocessor system

Binata Bhattacharyya; Chandra P. Joshi; Chung-Chi Wang; Liang Yin; Vivek Garg; Phanindra K. Mannava


Archive | 2006

System and method for a 3-hop cache coherency protocol

Phanindra K. Mannava; Robert Beers; Seungjoon Park; Brannon Baxton


Archive | 2008

Method and system for flexible and negotiable exchange of link layer functional parameters

Phanindra K. Mannava; Victor W. Lee; Aaron T. Spink


Archive | 2009

Interconnect architectural state coverage measurement methodology

Phanindra K. Mannava; Seungjoon Park; Ajit Dingankar; Ching-Tsun Chou; Nikhil Mittal; Radhakrishnan V. Mahalikudi; Mayank Singhal


Archive | 2004

Method and apparatus for power management in the link layer

Naveen Cherukuri; Sanjay Dabral; David S. Dunning; Tim Frodsham; Phanindra K. Mannava; Theodore Z. Schoenborn; Aaron T. Spink; Jeffrey R. Wilcox

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