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Featured researches published by Phil Geng.


electronic components and technology conference | 2004

Mechanical shock testing and modeling of PC motherboards

James M. Pitarresi; Brian Roggeman; Satish C. Chaparala; Phil Geng

Due to a variety of manufacturing, environmental, shipping, and end-use conditions, personal computer (PC) motherboards and other circuit boards may be subjected to potentially damaging mechanical shock loads. As these loads can lead to product failure, an understanding of the response of circuit boards subjected to suddenly applied loads is necessary. A first step in this direction is to develop and validate modeling approaches for the simulation of shock load response on PC motherboards. Since building a detailed model of the motherboard would be difficult due to the wide variation in length scales and localized concentrations of mass/stiffness due to components, two simplified modeling approaches were investigated: global property smearing and simple block modeling. Both of these methods approximate the influence of regions with widely differing stiffness and mass properties resulting from the placement of components, connectors and other items on the circuit board while simultaneously avoiding problems associated with developing large, expensive, detailed models. Both the shock response spectrum (SRS) method and an implicit direct integration (i.e., time-marching) scheme were used to simulate the shock response. In addition to modeling, programmed shock pulse and drop table measurements were carried out on the motherboard to validate and understand the limits of the finite element simulations. The results show that the predicted peak response at a number of locations on the motherboard correlated well with measurements made during the shock loading; however, improvements in the simple models are still required to strengthen their correlation. Surprisingly, the simple global smear approach produced good results with significantly less solution time than the block model. Finally, it was found that the SRS method significantly under predicted the response of the motherboard. This may be due to large displacements induced in the motherboard by the high-g shock loads.


electronic components and technology conference | 2002

Effect of strain rate on solder joint failure under mechanical load

Phil Geng; Philip H. Chen; Yun Ling

A four-point bend test fixture and a daisy-chained test coupon with BGA mounted at 45-degree orientation were developed to evaluate solder joint failure through a simple test and finite element modeling procedure. The bending test was performed under various loading speed. The BGAs tested have 1.27 mm and 1.00 mm pitches, respectively. One of the significant findings is that the solder joints failure is highly strain rate dependent. At higher strain rate, solder joint failed at much less board deflection for some BGAs. This indicates that the common practice of quasi-static bending test is not sufficient to quantify the solder joint failure under shock load.


electronic components and technology conference | 2005

Dynamic test and modeling methodology for BGA solder joint shock reliability evaluation

Phil Geng

This work developed a dynamic test and modeling methodology for BGA solder joint shock strength evaluation. A test board and a test fixture were designed similar to a four-point bend test. The test setup for BGA evaluation was calibrated to a typical desktop PC motherboard under packaged shock condition. The fundamental frequency of the proposed test setup is matched to that of the motherboard through the experimental modal analysis. The BGA solder joint shock failure envelope was established through the proposed shock test and modeling. With an incremental shock sequence and an in-situ solder joint continuity monitoring setup for the shock events, the G-level (acceleration) and shock duration at BGA solder joint failure was measured. The dynamic finite element analysis was performed with the experimental input and the test board dynamic response to the measured solder joint failure shock level was simulated. The failure strengths of the solder joints were estimated with different BGA orientations on the test board. A preliminary solder joint failures envelope under dynamic load is established, which represents key board and system levels shock conditions.


electronics packaging technology conference | 2003

Modal analysis for BGA shock test board and fixture design

Phil Geng; Willem M. Beltman; Philip H. Chen; George Daskalakis; David Shia; Michael Williams

This work serves to evaluate solder joint shock reliability for Intels desktop motherboard and OEM desktop systems. A component level dynamic test system was developed to represent motherboard system behavior and modal analysis was introduced to evaluate and calibrate the test board fundamental frequency. By mounting a mass to the test board, the test system was adjusted to simulate the BGA solder joint dynamic behavior at the motherboard and desktop system level. Modal testing was performed with various mounting masses on the test board, which represents designed heatsink masses on the motherboard. The resonance frequencies and the corresponding mode shapes of the test boards were measured. Finite element modal analysis was performed for the test board/fixture. Numerical results showed excellent agreement with the modal testing data. The testing/modeling data provides the ground work for the component level shock test and the solder joint dynamic failure strength evaluation.


electronic components and technology conference | 2006

Application of shadow moire technique to board level manufacturing technologies

Phil Geng; Tozer Bandorawalla; Steve Cho; Hank Hsiao; Jonathon Kuchy; Gary Long; Robert R. Martinson; Alan McAllister; Michael Mello; Karumbu Meyyappan; Richard L. Williams; Liping Zhu

Shadow moire technique is already well-established as a technique for evaluating component warpage. Improvements to the metrology have increased its usefulness for evaluating various board-level manufacturing technologies. This experiment used the technique for two key board-level applications: i) Bare printed circuit board (PCB) warpage during the lead-free reflow: PCB warpage is becoming more significant due to the higher temperature required for lead-free reflow. This work used shadow moire dynamic reflow simulation to explore the effect of three variables - board thickness, glass transition temperature, and vendors - on board warpage. The test data showed clearly that board thickness is the most significant variable; ii) Assembled board warpage under mechanical preload from thermal solutions and under thermal cycling: One of the heatsink design approaches for desktop motherboards is to apply a preload to the CPU area of a motherboard in order to ensure thermal performance. This approach requires a more careful control of the preload. Board warpage is significant and is identified as a good metrology for preload estimation. Motherboards under three different preloads in the CPU area were measured. Both the global board warpage and the local board warpage around the CPU area were measured for preload correlations. The measured board warpage was correlated to the board preload successfully. In addition to these two issues, other examples are discussed briefly to demonstrate the capability of the board level shadow moire technique. The work proved that the metrology has become an indispensable thermal-mechanical analysis for manufacturing technology evolutions


ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference | 2005

Shadow Moiré Evaluation of Motherboard Warpage Under Preload CPU Thermal Solutions

Phil Geng; Robert R. Martinson; Richard L. Williams; Michael Mello; Steve Cho

This work investigated the motherboard coplanarity and preload correlation using the shadow moire interferometry. Motherboards under three different preloads in the CPU area were examined at room temperature and elevated temperature. Both the global board warpage and the local board warpage around the CPU area were measured for preload and temperature correlations. The measured board coplanarity was correlated to the board preload successfully. The results clearly identified a failure mode from the outlier, which has totally different warpage shape and corresponds to the uneven preload case. Also, the creep effect under preload during heating stage was observed and quantified.Copyright


International Journal of Materials and Structural Integrity | 2014

Thermal fatigue life prediction of solder joints of plastic ball grid array packages

Yin Fun Chu; Sung Yi; Phil Geng

In the present study, the fatigue life of solder joints of plastic ball grid array packages (PBGA) under thermal cycling condition is evaluated using the finite element method. A unified, viscoplastic constitutive model for solder joints of plastic ball grid array packages is employed to improve accuracy of reliability prediction. The constitutive model is then implemented into the commercial finite element analysis software, ABAQUS, to predict the thermo-mechanical behaviour of solder balls in PBGA package subjected to thermal cycling. Damage parameters are obtained from the FEA results and are used to estimate the thermal fatigue life of solder balls. The Coffin-Manson equation is employed. The predicted thermal fatigue lives are discussed in detail.


intersociety conference on thermal and thermomechanical phenomena in electronic systems | 2004

Alternative lead-free solder joint integrity under room temperature mechanical load

Phil Geng; R. Aspandiar; Tiffany A. Byrne; F. Pon; Daewoong Suh; Alan McAllister; A. Nazario; P. Paulraj; N. Armendariz; T. Martin; T. Worley

This work explored the feasibility of using alternative lead-free solder alloy with lower melting temperatures as board-level interconnects and attempted to establish preliminary baseline reliability under mechanical loads. Solder ball pull and shear tests were first performed at package level. Bend tests were performed at board level with PCB/BGA test coupons under monotonic three-point bending load. In addition to the traditional Sn-Pb solder and current lead-free Sn-Ag-Cu solder, four other lead-free solders (Sn-In, Sn-Bi, Sn-Bi-Ag and Sn-Zn-Al) were tested. For the board level test, surface finishes were immersion silver (ImAg) and organic solderability preservatives (OSP) with package level surface finish of electrolytic Ni and electrolytic Au. The test coupon with surface mounted BGAs has both via-in-pad (VIP) pads and non-VIP pads. The pull, shear and bend test results showed that Sn-In solder has the lowest performance, while Sn-Bi and Sn-Bi-Ag solder compositions showed comparable performance to Sn-Ag-Cu. The work showed that Sn-Zn-Al solder could be a potential choice for lead-free solder alternative. Bend test showed that most of the BGAs with non-VIP pads performed better than those with VIP pads.


international conference on electronic materials and packaging | 2012

Effects of microstructure on thermal fatigue life prediction of solder joints

Hiue Tran; Yin Fun Chua; Sung Yi; Phil Geng

In the present study, effects of microstructure on the fatigue life of solder joints under thermal cycling conditions are evaluated using the finite element method. A unified, viscoplastic constitutive model for solder joints of plastic ball grid array packages is employed to improve accuracy of reliability prediction. The constitutive model is then implemented into the commercial finite element analysis software, ABAQUS, to predict the thermo-mechanical behavior of solder balls in PBGA package subjected to thermal cycling. Damage parameters are obtained from the FEA results and are used to estimate the thermal fatigue life of solder balls. The Coffin-Manson equation is employed. The predicted thermal fatigue lives are discussed in detail.


intersociety conference on thermal and thermomechanical phenomena in electronic systems | 2006

Impact of Enabling solution design on SLI reliability during Temperature Cycling using Shadow Moire

Karumbu Meyyappan; Phil Geng; Ife Hsu

The enabling solutions used in todays computer systems commonly apply some amount of preload on the socket/package. This load plays a critical role in modulating the reliability performance of the second level interconnects (SLI). The load manifests itself as a board warpage that can be quantified using techniques such as board level shadow moire (BLSM). This paper describes specifically the use of board level shadow moire as a viable and insightful technique for measuring the board warpage induced by a socket to enabling solution (ES) interaction. This paper also outlines thermal cycling experiments that have been conducted to study the impact of enabling solution on the thermal cycling performance. The empirical data from these thermal cycling experiments will be used to establish correlation to the areas of high curvature indicated by BLSM; Hence, validating its benefits

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