Alan McAllister

Effects of Glue on the Bend Performance of Flip Chip Packages

To combat reliability margin loss in ball grid array (BGA) packages specifically in mechanical shock and vibration testing, companies are exploring the possibility of using glue and complete underfill to mitigate risk to second-level interconnects (SLI). Though glue has been demonstrated to have a positive influence on SLI reliability margin, it can have adverse affects on the rest of the package such as substrate or first-level interconnects (FLI). This paper explains details on how glue modulates the overall reliability of the package. Finite-element modeling (FEM) along with low strain rate bend tests was done to prove the effect of glue on solder joint reliability. Further, shock testing was done to demonstrate how the glue modulates the shock performance. The improvement in SLI reliability was highly dependent on the choice of glue.

Flip chip ball grid array component testing under board flexure

With increasing attention on component damage caused by motherboard flexure during manufacturing processes, strain-based methodologies are being incorporated into component testing and manufacturing tool qualifications. While significant progress has been made in proliferation of these methodologies, some fundamental questions have not been sufficiently addressed. One of these is the nature in which bend mode impacts the relationship between board strain and forces or stresses acting on the solder ball. To understand this, a study into the effect of bend mode was performed. From a flexure experiment and a series of finite element models, it is shown that the point at which interconnects fail is associated with the mode in which the board is deformed. As a metric to measure board strain, maximum principal strain is very sensitive to bend mode. The diagonal strain metric can reduce, but cannot completely eliminate, bend mode sensitivity. Both the design of experiment (DOE) and the finite element models show that a planar bend mode in which the board has significant curvature in only one direction (e.g. four-point bend) is more benign than a mode in which the board has significant curvature in two orthogonal directions (e.g. twist and a spherical mode). In addition, it was found that a strain gauge placed on the substrate corner can be a very useful experimental tool in flip-chip ball grid array (FCBGA) component testing for the purpose of identifying the onset of cracking under lands on the PCB side. These key points have been successfully incorporated into the flexure testing methodology for FCBGA components at Intel.

Characterizing mechanical performance of Board Level Interconnects for In-Circuit Test

Lead Free boards are more susceptible to mechanical stress and therefore more prone to damage during manufacturing, assembly and field use. The IPC/JEDEC 9707(Spherical Bend Test Method for Characterization of Board Level Interconnects) was developed to characterize the mechanical performance of new lead free materials (i.e. laminates), board design features (i.e. pad design), and components (i.e. BGAs). This paper describes the application of the new IPC/JEDEC 9707 standard to qualify the mechanical performance of board interconnects for manufacturing and In-Circuit Test. The efforts of the International Electronics Manufacturing Initiative (iNEMI) Board Flexure Initiative Project team drove the development of this new IPC/JEDEC 9707standard.

Application of shadow moire technique to board level manufacturing technologies

Shadow moire technique is already well-established as a technique for evaluating component warpage. Improvements to the metrology have increased its usefulness for evaluating various board-level manufacturing technologies. This experiment used the technique for two key board-level applications: i) Bare printed circuit board (PCB) warpage during the lead-free reflow: PCB warpage is becoming more significant due to the higher temperature required for lead-free reflow. This work used shadow moire dynamic reflow simulation to explore the effect of three variables - board thickness, glass transition temperature, and vendors - on board warpage. The test data showed clearly that board thickness is the most significant variable; ii) Assembled board warpage under mechanical preload from thermal solutions and under thermal cycling: One of the heatsink design approaches for desktop motherboards is to apply a preload to the CPU area of a motherboard in order to ensure thermal performance. This approach requires a more careful control of the preload. Board warpage is significant and is identified as a good metrology for preload estimation. Motherboards under three different preloads in the CPU area were measured. Both the global board warpage and the local board warpage around the CPU area were measured for preload correlations. The measured board warpage was correlated to the board preload successfully. In addition to these two issues, other examples are discussed briefly to demonstrate the capability of the board level shadow moire technique. The work proved that the metrology has become an indispensable thermal-mechanical analysis for manufacturing technology evolutions

Fundamentals based approach to predict socket stack performance

The field performance of a separable socket/connector is governed by its ability to maintain the target contact resistance throughout its life. Contact resistance stability and protection against field degradation mechanisms is achieved by maintaining a critical normal force on the contact. With growing socket contact pin counts and package complexities there are challenges with achieving and maintaining this critical contact normal force across the array of contacts in the socket. In this effort, the authors characterized the key mechanical and resistance relationship (Force-Deflection-Resistance)through single contact resistance measurements. An analytical model of a socket stack was developed to better capture the contact normal force distribution across the contact array. The contact forces extracted from the analytical model were then converted to contact resistances through the Force-Deflection-Resistance relationship obtained from single contact resistance measurements. Force-Resistance variation from contact to contact was comprehended through a Bootstrapping technique. This fundamental based approach of using finite element, single contact data and statistics was then validated against fully enabled socket measurements using electrically daisy chained test vehicles.

Application of Projection Moiré in Electronic Packaging and Assembly for Post-Surface Mount Warpage Measurements

Geometric moire techniques, such as shadow and projection moire, are useful for quantifying the out-of-plane displacement, or warpage, of electronic packaging components at elevated temperature. While shadow moire is widely used for measuring the warpage of ball grid array (BGA) packages and bare printed circuit boards (PCB’s) with high accuracy and resolution, it is restricted by the need for a glass reference grating within close proximity to the sample. This prevents the capability from measuring surfaces varying largely in height, thus limiting the scope of study for deformations induced through the various stages of the electronic packaging, assembly and surface mount process. Projection moire uses virtual gratings of various sizes, making it an ideal technique for investigating large field depths and boards populated with components.

Alternative lead-free solder joint integrity under room temperature mechanical load

This work explored the feasibility of using alternative lead-free solder alloy with lower melting temperatures as board-level interconnects and attempted to establish preliminary baseline reliability under mechanical loads. Solder ball pull and shear tests were first performed at package level. Bend tests were performed at board level with PCB/BGA test coupons under monotonic three-point bending load. In addition to the traditional Sn-Pb solder and current lead-free Sn-Ag-Cu solder, four other lead-free solders (Sn-In, Sn-Bi, Sn-Bi-Ag and Sn-Zn-Al) were tested. For the board level test, surface finishes were immersion silver (ImAg) and organic solderability preservatives (OSP) with package level surface finish of electrolytic Ni and electrolytic Au. The test coupon with surface mounted BGAs has both via-in-pad (VIP) pads and non-VIP pads. The pull, shear and bend test results showed that Sn-In solder has the lowest performance, while Sn-Bi and Sn-Bi-Ag solder compositions showed comparable performance to Sn-Ag-Cu. The work showed that Sn-Zn-Al solder could be a potential choice for lead-free solder alternative. Bend test showed that most of the BGAs with non-VIP pads performed better than those with VIP pads.

Impact of corrosive environment on contact resistance of infrequently mated connectors

Separable connectors are commonly plated with gold for optimum electrical properties. In aggressive environments, gold provides adequate resistance for corrosion of underneath copper. Corrosion resistance has been historically studied by exposing the connectors to a mixture of corrosive gases through a mixed flowing gas (MFG) test. A few studies in the past claimed that contact electrical resistance can stay stable even in unplated samples if micromotion between the interfaces can be eliminated. However, contact force relaxation and micromotion can disturb the mating interface resulting in resistance increases. To understand the interactions between surface finish plating, end usage and micromotion under an aggressive environment, a DOE was planned with linear edge connectors in a MFG chamber. The effect of end usage was addressed through mated and unmated connector samples followed by electrical testing. The impact of mechanical force was studied by controlling the micromotion through a custom vibration fixture that was designed to operate within the MFG chamber. Results from our studies are expected to initiate efforts towards improving existing industry test standards with recommendation to consider the effects of mechanical retention and end usage in addition to plating material and thickness.

Thermal-Mechanical Impact of Thermal Solutions in Handheld Devices

Use of Thermal Interface Materials (TIM) is a common thermal solution approach in handheld devices to reduce junction temperature and control device skin temperature. This work summarizes the thermal benefits of using a TIM for enhancing the user experience and increasing System on Chip (SoC) performance. On the other hand, TIM induces a load on the package which in turn can impose stress on the package solder joints. This paper explains the impact of a variety of parameters such as TIM material and thickness and system boundary conditions on thermal performance of the SoC/system and the load distribution on solder joints. The complexity of mechanical load distribution is discussed through extensive data collection and simulation in phone and tablet form factors. Design guidelines for selection of appropriate TIM are proposed to improve the thermal performance without compromising the reliability of the SoC package.Copyright

Optimizing gold thickness of land grid array pads for cost, performance and reliability of connectors

Gold plated socket contact tips and substrate lands are commonly used in the electronics industry for optimum electrical properties. Increasing the gold thickness improves corrosion resistance and provides stable contact resistance at lower mechanical forces. However, with the ever increasing cost of gold it is critical to optimize the socket stack for cost, performance and reliability. To demonstrate this balance, a study on the stability of socket contact resistance was conducted at various gold thicknesses of substrate lands ranging from 60 to 400 nm using a single contact test setup. Contact forces were measured with a tri-axial force sensor that provided a means for extracting the coefficient of friction between the contact interface and substrate lands. An empirical model that relates the contact resistance to mechanical force and plating thickness was derived from the Force-Deflection-Resistance trends observed across various gold thicknesses. In this study, some of the plating options considered included a layer of Palladium (Pd) between the Nickel (Ni) and Gold (Au) layers to improve the corrosion resistance. The corrosion resistance was quantified by exposing the substrates to temperature, humidity and mixed flowing gas (MFG) chambers. The experimental findings could be used for optimization of the Gold plating thickness for cost, performance and reliability.