Philip Anthony

An Experimental Investigation of the Tradeoff between Switching Losses and EMI Generation With Hard-Switched All-Si, Si-SiC, and All-SiC Device Combinations

Silicon carbide (SiC) switching power devices (MOSFETs, JFETs) of 1200 V rating are now commercially available, and in conjunction with SiC diodes, they offer substantially reduced switching losses relative to silicon (Si) insulated gate bipolar transistors (IGBTs) paired with fast-recovery diodes. Low-voltage industrial variable-speed drives are a key application for 1200 V devices, and there is great interest in the replacement of the Si IGBTs and diodes that presently dominate in this application with SiC-based devices. However, much of the performance benefit of SiC-based devices is due to their increased switching speeds ( di/dt, dv/ dt), which raises the issues of increased electromagnetic interference (EMI) generation and detrimental effects on the reliability of inverter-fed electrical machines. In this paper, the tradeoff between switching losses and the high-frequency spectral amplitude of the device switching waveforms is quantified experimentally for all-Si, Si-SiC, and all-SiC device combinations. While exploiting the full switching-speed capability of SiC-based devices results in significantly increased EMI generation, the all-SiC combination provides a 70% reduction in switching losses relative to all-Si when operated at comparable dv/dt. It is also shown that the loss-EMI tradeoff obtained with the Si-SiC device combination can be significantly improved by driving the IGBT with a modified gate voltage profile.

High-speed resonant gate driver with controlled peak gate voltage for silicon carbide MOSFETs

Parasitic inductance in the gate path of a Silicon Carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimental results for a 1200 V Silicon Carbide MOSFET gate driver are presented, demonstrating switching loss of 230 µJ at 800 V, 10 A. This represents a 20% reduction in switching losses in comparison to conventional gate drive methods.

A First Approach to a Design Method for Resonant Gate Driver Architectures

This paper proposes a general circuit model and design method for resonant gate drivers. Topologies in the literature are analyzed by dividing each switching transient into up to five energy transfer stages, for which general analytical equations are derived. A general resonant gate driver circuit model is presented. Several reviewed topologies are identified as unique combinations of current paths within this circuit model, providing a basis for classification. This establishes a relationship between topology performance and architecture, which is verified experimentally using a reconfigurable test circuit.

High-Speed Resonant Gate Driver With Controlled Peak Gate Voltage for Silicon Carbide MOSFETs

Parasitic inductance in the gate path of a Silicon Carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimental results for a 1200 V Silicon Carbide MOSFET gate driver are presented, demonstrating switching loss of 230 μJ at 800 V, 10 A. This represents a 20% reduction in switching losses in comparison to conventional gate drive methods.

High-Efficiency NPC Multilevel Converter Using Super-Junction MOSFETs

Super-junction MOSFETs exhibit low on-state resistances and low switching losses. However, the reverse recovery behavior of their intrinsic diodes and their output capacitance characteristics make their deployment in freewheeling locations challenging. In this paper, a new snubber circuit arrangement has been proposed for a three-level converter to minimize the effect of the output capacitance. This is used in conjunction with diode deactivation circuitry to address the diode recovery behavior. Results are given for a three-phase three-level neutral point clamped converter running from an input voltage of 720 V and supplying a 3-kVA load. The converter operates with no forced cooling and efficiency is estimated at 99.3%. Apart from lower energy consumption, an advantage of high efficiency is a reduced converter mass due to reduced cooling requirements.

Figure of merit for selecting super-junction MOSFETs in high efficiency voltage source converters

Silicon super-junction MOSFETs have very low on-state resistances and fast switching characteristics. However, their use in voltage-source converters is hindered by the poor reverse recovery performance of their body drain diode and an adverse output capacitance characteristic. These both act to increase the overall switching loss. The on-state resistance and output capacitance characteristics of super junction devices are both related to the area of the silicon die. As this increases, the on-state resistance decreases but the output capacitance increases. A figure of merit is evaluated with both predicted and experimental results using a 400-V, DC-DC synchronous buck-converter operating over a range of output currents and switching frequencies.